SU1260964A1 - Device for visual checking of program execution - Google Patents

Abstract

This invention relates to automation and computing. The aim of the invention is to increase speed. To achieve the goal, a device containing a register of the current address G, a multiplexer 3, an indication block 9, a comparison block 7, and a mode setting block 2 and addresses are entered into the initial 4 and end 5 address registers, the code-voltage converter 8 and the state register 6 niy 3 il. Yu Oh o so 05 4

Description

This invention relates to automatics and computing.

The purpose of the invention is to increase the

FIG. 1 is a block diagram of the deviceJ of FIG. 2, 2 is a diagram of a keyboard and a multiplexer of FIG. 3 is a diagram of a comparison unit,.

The device for visual control of program execution contains the current address register 1, the mode setting unit 2 and the address, multiplexer 3, the start 4 and end address 5 registers, the status register 6, the comparison unit 7, the code converter 8, the voltage, the display unit 9, bus 10 addresses, input 11 synchronization and input 12 status signals.

Register 1 of the current address is designed to memorize the current address at times determined by pulses from the multiplexer 3. Its width corresponds to the bus width of the address of the computer, Keyboard 2 is used to set the address, control registers 4 and 5 by multiplexer 3, Multiplexer 3. Designed for generating control pulses at times determined by the position of toggle switches on the keyboard.

Registers 4 and 5 of the starting and ending addresses store the corresponding

addresses defining the beginning and end of the fragment operator of interest

, programs. The state register 6 is intended for storing information describing the state of the processor (selecting a command from the ROM, accessing the stack, accessing external devices, etc.). Comparison block 7 performs a comparison of the codes of the current address with the codes of the starting and ending address and generates a pulse, the duration of which corresponds to the running time of the checked program fragment. The converter 8 code-voltage is intended to transform the code of the current address into an analog signal-. The display unit 9 serves to graphically display the execution of the program.

Registers 1, 4-6 devices have an identical structure and can be executed on D-triggers, D-inputs of which are information inputs of registers, and synchronization inputs are combined and serve as a synchronous input of registers, direct outputs of triggers are outputs of registers. When implementing blocks 1, 4-6, ready-made registers can be used, for example, 133IR135IPIR9 in typical switching circuits,

The set of tasks, modes and addresses contains a group of 13 buttons, a group of 14 RS-flip-flops, pythrator: 159 registers 16–19, a group of 20 toggle switches for selecting states, buttons 21 and 22 for recording start and end addresses.

Multiplexer 3 consists of a group of 23 elements 2I-NOT and an element 5I-NOT 24,

Comparison unit 7 contains two comparison circuits 25 and 26 and IV5-flip-flop 27, as the comparison circuits of codes, 56IP2 microcircuits can be used, and the necessary size in this case is achieved by cascading several chips

Converter In the code-voltage can be performed on the chip 572PA1 in its standard inclusion.

The display unit 9 may be an oscilloscope having a vertical deflection input (input 1 of unit 9).

The device works as follows.

The information input of the 6 state register is received from a computer signals characterizing the current state of the processor, and the synchronization input is sent to processor synchronization pulses, which register the current state of the processor to register 6. As the state of the processor varies with its internal clock, t, and, with each period of sync pulse, each pulse output of register 6 generates a sequence of pulses corresponding to certain moments of the computer operation: addressing the first byte, t, e, past command, access to external devices, access to RAM, etc. All the generated sequences are fed to the inputs of the 2I-NO 23 multiplexer 3, but only those of them that are selected by the operator using the keyboard 20 toggle switches pass through to its output. After convolution by OR, the resultant clock sequence is fed to the synchronous register 1 of the current address

sa The address input of the processor is connected to the information input of this register, and at its output a sequence of addresses displaying the necessary information for the operator: the sequence of selecting commands from the ROM, and the sequence of calls to the RAM, and any combinations of address addresses of the processor. This sequence of addresses is converted by the code-voltage converter 8 and fed to the display unit 9, for example, an oscilloscope, which presents the information to the operator in the most convenient for perception graphical form.

The proposed device provides for the possibility of separating an arbitrary program fragment, for example, by highlighting a part of a graphic image. For this, the operator, by successive pressing of the buttons 13, after passing the signal through the anti-pounding triggers 14 and the encoder 15, writes the required address (determining the initial and final address of the program fragment in question) to the keyboard 2 buffer memory (registers 16-19). rewritten to register 4 or 5 by pressing buttons 21 or 22, respectively. Codes from registers 4 and 5 are fed to the inputs A of the comparison circuits 25 and 26, to the input of which the current address code is supplied. When comparing the codes present at their inputs, blocks 25 and 26 output pulses, which go to the setup inputs R 5 of the trigger 27. At the output of the trigger 27, a pulse is generated, the temporary position and duration of which corresponds to the program fragment selected by the operator. This pulse arrives at the second input of the display unit 9, which uses it to extract the desired fragment from the information coming through the first input.

So, when using an oscilloscope as a recording unit, the second input of which is a beam brightness modulation input, the program section is counted on the CRT screen, and when using an external synchronization channel as an input, the program is displayed not from zero, but from some initial shy in

register 4. Regulating the duration of the sweep: an oscilloscope and choosing the starting and ending addresses, you can examine the fragment of the program with any degree of detail.

The proposed device for visual control can significantly increase the speed of debugging programs and significantly increase the information content.

Claims (1)

Invention Formula A device for visual control of program execution, containing-; the current address register, a multiplexer, a display unit, a comparison unit and a mode setting unit and an address, wherein the current address register output is connected to the first information input of the comparison unit, the first address output of the mode setting unit and the address is connected to the multiplexer control input that, for the purpose of defending speed, the registers of the initial and final addresses, the code-voltage converter and the status register are entered into it, the second address output of the mode setting block and the address connected to the information inputs of the initial and final address registers whose outputs are connected to the second and third information inputs of the comparison block , the output of the comparison unit is connected to the synchronization input of the display unit; the device’s address input is connected to the information input of the code-voltage converter, the output of which is connected to the information input of the display unit; the information input and the synchronization input of the device are connected respectively to the information and clock inputs of the status register; which is connected to the information input of the multiplexer, the output of which is connected to the input of the record of the current address register, the first and second modes Reference mode block outputs the address and the registers respectively connected to inputs recording start and end addresses. Editor L. Pchelinska Compiled by I. Sigalov Tehred M, Morgent Proofreader M. Maximipschnetz Order 5760, Circulation 671: Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, R. Uzhgorod, st. Project, 4 (rig. 3