SU1550604A1 - Shaper of signals of special shape - Google Patents

Abstract

The invention relates to a pulse technique and can be used in automation and measuring devices. The purpose of the invention is to enhance the functionality by enabling the formation of trapezoidal, trapezoidal-triangular and saw-tooth stresses. For this, a driver containing input keys 1, 22, keys 13, 17, 27, 29, 36, 38, adders 6, 19, storage elements 4, 7, output keys 8, 9, RC circuits 14, 18, resistors 28, 37, counters 20, 30, elements NOT 24, 33, 34, elements AND 23, 31, elements OR 12, 16, input voltage source 3, clock generator 5, elements BAN 10, 11, 15, 21, 25 , 32, introduced switches 39, 47, 54, 56, element I 49, counters 40, 48, 57, triggers 43, 60, display element 44, one-shot 41, 50, 58, 61, elements OR 26, 35, 42, 51, 59, keys 45, 52, 53, resistor 62, BANKS 46, 55 elements. Trapezoidal, trapezoidal-triangular and sawtooth Voltage is generated on the bus 64 from a triangular voltage generated on the bus 63 by closing the key 53 for the required time interval. When forming trapezoidal voltage, the beginning of the specified time interval is determined by filling the counter 48, and the end of the interval is filling the counter 57. When forming trapezoidal-triangular voltage, the beginning of the interval is determined by the counter 48, and the end of the interval is determined by the counter 40. When forming the saw-tooth voltage, the duration of the interval is determined by the counter 57. 5 Il.

Description

The invention relates to a pulsed technique and can be used in automation and measuring devices.

The purpose of the invention is to expand the functional capabilities of the device by enabling the formation of keystone, keystone-triangular stresses and sawtooth voltage.

Figure 1 shows the structural scheme of the proposed device; figure 2 5 shows timing diagrams explaining the operation of the device.

The device contains the first input key 1, the first switch 2, the source 3 of the input voltage, the first storage element 4, the clock generator 5, the first adder 6, the second storage element 7, the first and second output keys 8 and 9, the first and the second BANNER elements 10 and 11, the first element OR 12, the first key 13 the first KS circuit 14, the third element BANKS 15, the second element OR 16, the second key 17, the second KS circuit 18, the second adder 19, the first pulse counter 20, the fourth element BAN 21, second input key 22, first element AND 23, first element NOT 24, fifth ele cop BAN 25, the third element OR 26, the third key 27, the first limiting resistor 28, the fourth key 29, the second counter 30 pulses, the second element And 31,

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the sixth element of the PROHIBITION 32, the second and third elements are NOT 33 and 34, the fourth element OR 35, the fifth key 36, the second limiting resistor 37, the sixth key 38, the second switch 39, the third counter 40 pulses, the first single vibrator 41, the fifth element OR 42, the first trigger 43, the display element 44, the seventh key 45, the seventh element BANGE 46, the third switch 47, the fourth pulse counter 48, the third element AND 49, the second one-shot 50, the sixth element OR 51, the eighth and ninth keys 52 and 53 , the fourth switch 54, the eighth element BANKS 55, the fifth switch 56, the fifth circuit a pulse 57, a third one-shot 58, a seventh-element OR 59, a second trigger 60, a fourth one-shot 61, a third limiting resistor 62, the first and second output buses 63 and 64, the setpoint bus 65 of the initial state. The input of the first input key 1 through the fifth switch 56 is connected to the source 3. The inputs of the first and second output keys 8 and 9 are connected respectively to the outputs of the first and second storage elements 4 and 7, and the outputs are connected to the first input of the first adder 6, the second input of which connected to the output of the first input key 1, and the output connected to the inputs of the first and second storage elements 4 and 7. The control

the inputs of the first output key 8 and the second storage element 7 are connected to the first output of the clock generator 5, and the control inputs of the second output key 9 and the first storage element 4 are connected to the second output of the clock generator 5. The output of the second element 11 is connected to the control input of the input key 1, the direct input is with the first output of the clock generator 5, the inverting input is with the inverting input of the third element 15, the direct input of which is connected to the direct input of element 11, and the output is connected to the second input of the sixth element OR 51, the output of which is connected to the control input of the second key 17, which is connected in parallel to the capacitor of the second RC circuit 18, the input of which is connected to the input of the input key 1. The sixth element 32 of the direct input is connected to the second output of the clock generator 5, and the output with the second input of the seventh element OR 59, the first input of which is connected to the first input of the element OR 51, and the output to the control input of the first key 13 connected in parallel with the capacitor of the first RC circuit 14, the input of which is connected to the input of the second RC circuit 18. The second adder 19 tr Another input is connected to the output of the memory element 4, the fourth input is connected to the output of the memory element 7. The counting input of the first counter 20 is connected to the first output of the clock generator 5, the inverse output is connected to the inverting input of the first element 10, the output of which is connected to the control input of the second input key 22, the input of which is connected to the input of the input key 1. The direct input of the element 10 is connected to the first output of the clock generator 5, with the direct input of the element 11, to the first input of the first element I 23, the second input of which is connected en with the inverting input of the second element 11, with the direct output of the counter 20 and through the first element NOT 24 with the direct input of the fourth element 21, the output of which is connected to the second input of the first element OR 12, the first input of which is connected to the output of the first element And 23, and the output from the control input of the fourth key 29, the output of which is connected to the second input

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adder 19, and the input is connected to the output of the second RC circuit 18 and through the first limiting resistor 28 and the third key 27 connected in series with the zero bus, the control input of the switch 27 is connected to the output of the AND 23 element. The second counter 30 is connected to the second output clock generator 5, the direct output of the counter 30 is connected to the inverting input of the element 32, to the inverting input of the element 21 and to the first input of the second element AND 31, the second input of which is connected to the second output of the clock generator 5, and the output to the direct input of the fifth email 25, the inverting input of which is connected to the output of the second element HE 33, the input of which is connected to the forward output of the counter 20, the third element NOT 34 to the input connected to the direct output of the counter 30, and the output to the first input of the second element OR 16, the second input which is connected to the output of the element 25, and the output to the control input of the fifth key 36, the output of which is connected to the first input of the adder 19, and the input to the output of the first RC circuit 14, and through the serially connected second limiting resistor 37 and the sixth key 38 with a common bus. The control input of the sixth key 38 is connected to the output of the element 31. The first output of the clock generator 5 is connected via the third switch 47 to the counting input of the fourth counter 48, the direct output of which through the first single vibrator 41 is connected to the first input of the third element OR 26, the output which is connected to the zero input of the first flip-flop 43, the direct output of which is connected to the element 44, and the inverse output to the control input of the ninth key 53. The seventh element 46 of the direct input is connected to the second output of the clock generator 5, which inverts the input is with the inverted output of counter 20, and the output through the first switch is the 2nd counting input of the third counter 48, the direct output of which is connected to the first input of the third element And 49, the second input of which is connected to the direct output of the counter 48, and the output through the second the one-shot 50 with the first input of the fourth element OR 35, the output of which is connected to the control input "

clock generator house 5, with the first inputs of the elements OR 51 and 59, with the inputs for setting to zero counters 20, 30, 40, 48, with the single input of the trigger 43 and with the control inputs of the seventh and eighth keys 45 and 52 and with the inputs connected in parallel the capacitors of the storage elements 4 and 7. The first output of the clock generator 5 through the second switch 39 is connected to the direct input of the eighth element 55, the output of which is connected to the second input of the element OR 26. The first output of the clock generator 5 is connected through the fourth switch 54 to the counting input n n 57, whose input to zero is connected to the output of the OR 35 element, and direct output through the third one-shot 58 to the second input of the fourth element OR 35, to the first input of the fifth element OR 42, the second input of which is connected to the third input of the fourth element OR 35, and the output - with a single input of the second trigger 60, the inverse output of which is connected to the inverting input of the BANNER element 55, and the zero input through the fourth one-shot 61 is connected to the inverse output of the trigger 43. The output of the adder 19 through serially connected third limiting resistor 62 and a ninth switch 53 is connected to a second output bus 64 of the device. The first output bus 63 is connected to the output of the adder 19. A bus 65 for setting the initial state of the device is connected to the third input of the fourth element OR 35.

The device works as follows.

The clock generator 5 generates two pulse voltages that are shifted relative to each other (Fig. 26c). The pulse voltage (Fig. 26) controls the operation of the output key 8, the key of the second storage element 7, through the elements 10 and 11, the operation of the input keys 22 and 1, through the sequence of elements 15 and 51, the operation of the key 17, through the element 23 and the operation of the key 27 , and through the elements AND 23 and OR 12 - the operation of the key 29.

The impulse voltage (Fig. 2c) controls the operation of the output key 9, the key of the first storage element

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This 4, through element 32 and the element OR 59 - by the operation of the key 13, through the element AND 31 - by the operation of the key 38, and through the sequence of elements AND 31, the element 25 and the element OR 16 - by the operation of the key 36.

In the presence of positive pulses at the outputs of the clock generator 5, the keys are closed, and if there are no pulses, they open. The adder 6 for each input has a single transfer coefficient.

Before starting work, to set the device to its initial state, a short pulse is applied to the bus 65

(Fig. 2a; 4a), under the action of which the clock generator 5 is set to its initial state through the OR 35 element, the keys 45 and 52 are triggered and the capacitors of the memory elements 4 and 7 are discharged, the trigger 43 is set to one, resulting in element 44, and on the inverse output of the trigger 43 a logical zero is set (fig. 3b; 4b; 56), counters 20, 30, 40, 48, f 57 are set to zero, and additionally the elements OR 51, 59 pass; the operation of the keys 13 and 17, which discharges the capacitors of the KS circuits 14 18, respectively. Passing the OR 42 element, the setting pulse arrives at the single input of the trigger 60, as a result of which the inverse output of the trigger 60 is set to a logical zero (fig.5d), which enters the inverting input of the element 55 and does not affect its triggering.

When the counter 20 is set to zero, a logical unit is set at its inverse output, which is fed to the inverting input of the element 10 and prohibits it from running. At the direct output of the counter 20, a logical zero is set, which arrives at the inverting inputs of elements 11 and 15 and does not affect their operation, which ensures the passage of pulses (Fig. 26) to the control inputs of keys 1 and 17. Pass through the element NOT 24 , this signal in the form of a logical unit is fed to the direct input of the element 21, which is triggered and passes the signal of the logical unit to the second input of the element OR 12, since

on the inverting input element 21 there is a logical zero signal from the direct output of counter 30. Pass through the element OR 12, the logical unit goes to the control input of the switch 29, which operates and connects the output of the RC circuit 18 to the second input of the adder 19. Pass through the element NOT 33, the logical zero from the direct output of the counter 20 as a logical unit enters the inverting input of the element 25 and prohibits it from triggering. The logical zero signal from the direct output of the counter 30 is fed to the inverting input of the element 32 and does not affect its operation, which ensures the passage of pulses (Fig. 2b) to the control input of the key 13, and passes through the element 34, arrives as a logical units to the first input of the element OR 16. Under the action of the logical unit from the output of the element OR 16, the key 36 is activated and connects the output of the RC circuit 14 to the first input of the adder 19.

The device provides the formation of a triangular voltage; the formation of trepseineal-triangular stress; trapezoidal stress formation; the formation of a sawtooth voltage with a fixed amplitude.

To form a triangular voltage, switch 56 is turned on, and switches 2, 39, 47, 56 are turned off. Upon receipt of the first control pulse (Fig. 26), the keys 1 and 8 and the key of the storage element 7 are closed, and the pulse itself is recorded in the counter 20. At the output of the adder 6, the voltage U is set. The capacitor of the storage element 7 is then output through a small output impedance 6 is charged before the voltage U. The parameters of the circuit are chosen so that the relations

(12)

With R - output impedance of the adder 6;

the capacitance of the capacitor in the storage elements 4 and 7;

control pulse duration;

l with

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R ъ% - input impedance. Matching amplifier in the storage elements.

When inequality (1) is fulfilled, the voltage to which the capacitor is charged does not depend on the change in its capacitance value, and when inequality (2) is fulfilled, the voltage remains unchanged during the time when the key of the storage element 7 is open. Thus, during the first period of the control pulses, the voltage at the output of the storage element 7 remains unchanged and equal to U (Fig. 2d).

Upon receipt of the second control pulse (Fig. 2b), the key 9 and the key of the storage element 4 are closed, and the keys 1 and 8 and the key of the storage element 7 are opened, and the pulse itself is written into the counter 30. The voltage, equal to U, from the output of the storage element 7 through the switch 9 enters the first input of the adder 6, and the capacitor of the storage element 4 is charged until the voltage U. The output at the output of the storage element 4, equal to U, remains unchanged during the follow-up period of the guide pulses (Fig. 2e).

Next, the keys 1 .and 8 and the key of the storage element 7 are closed again. At the same time, a voltage equal to 2 U is set at the output of the adder 6, since the voltage equal to U is supplied to the first and second inputs of the adder 6 via keys 8 and 1. The output from the adder 6 is recorded by the memory element 7, at the output of the matching, the amplifier of which is set to a voltage of 2 U (Fig. 2d). At the next cycle, this voltage is again rewritten into the storage element 4 (fig.2d).

Further, the processes are repeated with a period of 2t. As a result, step voltages are shifted at the outputs of the storage elements 7 and 4, shifted by a time Ј, and counters 20 and 30 are filled.

The step voltages (Fig. 2d; d) from the outputs of the storage elements 4 and 7 are fed to the inputs of the adder 19. When these voltages are combined, a new step voltage is formed on the adder 19, the slope of which is two times greater than the slope of the sum of the voltages ( fige). Besides,

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during the periodic closure of the keys 13 and 17, under the action of the control pulses of the clock generator 5, sawtooth voltages are formed on the capacitors of the RC circuits 14 and 18 (Fig. 2h; l) with amplitude Un.

For proper operation of the circuit, the parameters of the adder 19 are chosen so that the following relations are satisfied:

TO

Where

Un K

.k „.ip to –i to„ –and

- CL and and "transfer coefficients of the adder 19 for the corresponding inputs; input voltage amplitude; the amplitude of the voltage to which the capacitors of the RC circuits 14 and 18 are charged during time C. The time constant of RC circuits 1A and 18 is selected so that only the initial portion of the capacitor charge exponent is used and, the voltage at the outputs of the RC circuits is linear. In this case, by summing the step voltage (Fig. 2e) with sawtooth voltage (Fig. 2g; h). By entering respectively the first and second inputs of the adder 19, a linearly increasing voltage is obtained (Fig. E) taken from output adder 19.

After the input of the counter 20 pulses, where n is the number of bits of the setter 20, on pr -. At the output of the counter 20, a logical unit appears, which arrives at the inverting inputs of elements 11 and 15 and prohibits their triggering, and arriving at the second input of the element I 23, prepares its operation. At the inverse output of the counter 20, a logical zero signal is set, which is fed to the second inverting input of the element 10 and does not affect its operation. Starting from this moment, the pulses (Fig. 26) arrive at the control input of the input key 22, and the control input of the input key 1 arrives at a logic zero level. In addition, the logical unit from the direct output of the counter 20, having passed through the element NOT 24, in the form of a logical zero goes through elements 21 and 12 to yn the equal input of the key 29, which

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opens and shuts off the output of the RC circuit 18 from the second input of the adder 19.

After a pulse 30 arrives at the input of the counter (the width of the n counters 20 and 30 is the same), a logical unit appears at the forward output of the counter 30, which arrives at the inverting input of the element 32 and prohibits its triggering, and also enters the first input of the And 31 element and prepares its operation, and passes through the element NOT 34, in the form of a logical zero through the element OR 16 enters the control input of the key 36, which opens and turns off the output of the RC circuit 14 from the first input of the adder 19,

The output of the input key 22 is connected to the inverting input of the amplifier included in the adder 6. As a result, during each clock cycle, the voltage on the storage capacitors of the storage elements 4 and 7 is reduced by the value of U (Fig. 2d; d).

A falling portion of the step voltage is formed at the output of each of the storage elements 4 and 7 at the output of the adder 19 (Fig. 2e). Moreover, each time a pulse arrives (fig. 2b), the key 27 triggers on the first input of the element 23, since the second input of this element contains the signal of a logical unit from the direct output of the counter 20, and also through the element OR 12 the key 29 operates, the pulse time (Fig. 26) is the output of the RC circuit 18 to the second input of the adder 19. As a result, the discharge voltage of the capacitor of the RC circuit 18 goes to the second input of the adder 19 (Fig. 2k).

Similarly, when pulses (Fig. 2b) are received at the second input of the And 31 element, the key 38 is triggered, since the first input of the And 31 element contains the signal of a logical unit from the forward output of counter 30. At the same time, the signal of the logical unit from the output of the And 31 element to the first input of the element 25, which operates and passes the signal of the logical unit to the second input of the element OR 16, since the second inverting input of the element 25 contains a logical zero from the output of the HE element 33 and does not affect its operation. Under the action of the logical unit from the output of the element OR 16, the switch 36 operates and for the duration of the pulse (fng.2c) the output of the RC circuit 14 to the first input of the adder 19. As a result, the discharge voltage of the capacitor of the RC circuit 14 is fed to the first input of the adder 19 (Fig.2i).

The parameters of the constant discharge time through the switch 27 and the resistor 28 of the RC circuit 18 and through the switch 38 and the resistor 37 of the RC circuit 14 are selected so that the voltage at the outputs of these circuits is linear and symmetrical with the charging voltage of these circuits ( ; k; and) As a result, summing up the step voltage (Fig. 2e) with saw-tooth voltages (Fig. 2k; and) arriving at the inputs of the adder 19 results in a feed section of the linearly varying voltage (Fig. 2e). .

After the arrival of 2 ° pulses on the meters 20 and 30, the voltages on the capacitors of the memory elements 7 and 4 are reduced to zero, and the meters 20 and 30 are set to the original zero state. At the same time, when the counter 20 is set to the zero state and the logical unit appears at the output of the element NOT 24, the key 29 does not work, since at this time the logical unit enters the inverting input of the element 21 and prohibits its activation. In addition, the logical zero signal from the direct output of the counter 20, having passed through the element NO 33, in the form of a logical unit enters the inverting input of the element 25 and prohibits its triggering. As a consequence, the 2nth pulse, which passed to the counter 30 and set it to the zero state, passes to the key 38 and is not transmitted to the key 36, which remains in the open state after passing the 2n-1th pulse. In this case, the capacitor of the RC circuit 14 is discharged, and the capacitor of the RC circuit 18 is charged, but the voltage from their outputs is not fed to the inputs of the adder 19, the output of which remains for a duration of control pulses zero voltage 30 returns to the zero state; the circuit returns to the initial state, except that

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that at the output of RC circuit 18 there is a voltage of Un, but at the time of the appearance of the first pulse (Fig. 26), when a triangular voltage cycle is formed, this circuit is discharged, which does not affect the operation of the circuit (Fig. 2k) .

Upon the subsequent arrival of clock pulses, the processes are repeated in a similar way, as a result of which symmetrical step voltages are formed at the outputs of the storage elements 7 and 4, and a symmetrical triangular voltage is formed on the output bus 63. When an LED indicator is connected to the inverse output of the counter 30, it is possible to visually monitor the operation of the device. I

To form a trapezoidal-triangular voltage, the switches 2, 56 and 47 are turned on, and the switches 54 and 39 remain in the off state.

After setting the circuit to the initial state and the arrival of pulses from the outputs of the clock generator 5, a triangular voltage is formed at the output of the adder 19 (Fig. 2e). Simultaneously from the pulses (Fig. 26) of the clock generator 5, the switch 48 begins to fill the counter 48. At the same time, the signal of the logical unit from the inverse output of the counter 20 enters the inverting input of the element 46 and prohibits its operation, as a result of which the pulses (Fig. 2c) the output of the clock generator 5 is not received at the input of the counter 40, and it remains in the zero state.

After filling the counter 48 on. its direct output via signal is a logical unit that arrives at the second input of the And 49 element and prepares its triggering, as well as enters the input of the one-vibrator 41, which operates and generates a pulse at the output (FIG. 3a), under the action of which OR 26 the trigger 43 is triggered and set to the zero state, as a result of which the inverse output of the trigger 43 is a logical unit signal (Fig. 3b), under the action of which the switch 53 closes and the voltage from the output of the adder 19 through the resistor 62 and the switch 53 post Paet on output

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bus 64, and the front of a trapezoidal-triangular voltage is formed (Fig. 3g). At the moment when the logical zero is established at the inverse output of the counter 20, the element 46 opens, and from the pulses (Fig. 2b) of the clock generator 5, through the element 46 and the switch 2 begins to fill the counter 40.

After the counter 40 is filled, at its direct output the signal of a logical unit that goes to the first input of the element 49, which is triggered, since at its second input there is a logical unit from the output of the counter 48. On the leading edge of the voltage of the logical unit from the output element And 49, a one-shot 50 is triggered and generates a pulse at the output (Fig. 3b), which goes to the first input of the element OR 35, and when it passes, it goes to the single input of the trigger 43, which is set to one, resulting in second inverse output signal is set to logic zero (Figure 36), which is opened by the action of the key 53 and the trailing edge is formed trapezoidal-triangular voltage (fig.Zg).

At the same time, the impulse (fig.Sv), having passed the OR element 35, sets the counters 20, 30, 40 and 48 to the zero state, sets the clock generator 5 to the initial state, goes to the control inputs of the keys 45 and 52, which temporarily the action of the pulse is closed and discharges the capacitors of the storage elements 4 and 7. In addition, after passing through the elements OR 51 and 59, the pulse is supplied respectively to the control inputs of the keys 17 and 13, which are closed and discharged by the RC circuit capacitors 18 and 14. Thus, the circuit elements form l returned to its original state and the next cycle of the clock generator 5 starts the formation of the next-trapezoidal triangular voltage (fig.Zg).

To adjust the amplitude of the leading and trailing edges of a trapezoidal-triangular voltage, the number of bits of the counters 48 and 40, respectively, is changed.

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The pedal voltage switches on switches 56, 47 and 54, and switches 2 and 39 remain in the off state.

After setting the circuit to the initial state and the arrival of pulses from the outputs of the clock generator 5, the voltage is generated at the output of the adder 19 (Fig. 2e). At the same time, from the first pulse voltage (Fig. 2b), the counter 48 begins to fill the counter 48, and the counter 57 fills through the switch 54.

After filling the counter 48, the voltage of the logical unit appears at its direct output, under the action of which the one-shot 41 operates and generates at its output a pulse (Fig. 4b), which is fed to the first input of the OR 26 element. the impulse goes to the zero input of the trigger 43, which is set to the zero state, as a result of which its logical output is set to the logical unit (Fig. 4c), under the action of which the switch 53 closes, and the voltage from the output of the adder 19 through the resistor 62 and key 53 enters the output bus 64, and the leading edge of the keystone voltage is formed (FIG. 4e).

After filling the counter 57, a logical unit signal appears at its direct output, under the action of which the one-shot 58 is triggered and generates a pulse at the output (fig.4g), which enters the second input of the OR element 35 and passes it to the unit the input of the trigger 43, which is triggered and set to one state, as a result of which its inverse output is set to a logical zero (Figure 4b), under the action of which the key 53 is opened and the trailing edge of the trapezoidal voltage is formed (Figure 4e) "

At the same time, the pulse (Fig. 4d), the OR 35 element passed, enters the inputs of the installation of the counters 20, 30, 57 and 48 at zero and sets them to the zero state, sets the clock generator 5 to the initial state, enters the control inputs of the keys 45 and 52, which close and discharge the capacitors of memory elements 4 and 7 for the duration of the action of the said pulse, and

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through the elements OR 51 and 59, goes to the control inputs of the keys 17-13, which operate and discharge the capacitors of the RC circuits 18 and 14. Thus, the circuit elements of the driver return to their original state, and from the next cycle of the clock generator 5 begins the formation of the next trapezoidal voltage (figd).

To adjust the amplitude of the leading and trailing edges of the trapezoidal voltage, the number of bits, respectively, of the counters 48 and 57 is changed. Switches 39, 54 and 56 are turned on for forming the sawtooth, and switches 2 and 47 remain in the off state.

After setting the circuit to the initial state and the arrival of pulses from the outputs of the clock generator 5, the voltage is generated at the output of the adder 19 (Fig. 2e). Moreover, the first control pulse (Fig. 26) goes through the switch 39 to the direct input of the element 55, which passes the specified pulse to its output, since the inverting input of the element 55 contains a logical zero signal from the inverse output of the trigger 60 (Fig. 5e) . Then, the control pulse 26 (26a) is passed to the zero input of the flip-flop 43, which is triggered, as a result of which its inverse output appears the signal of the logical unit (FIG. 56), under the action of which the key 53 closes, the voltage from the output of the adder 19 through the resistor 62 and the key 53 is fed to the output pin 64 (Fig. 5e), and the leading front of the sawtooth is formed.

At the same time, the logical unit from the inverted output of the trigger 43 (Fig. 56) is fed to the input of the one-shot 61, which is triggered and generates a pulse at the output (Fig. 5b), which goes to the zero input of the trigger 60 and sets it to the zero state, due to what at the inverse output of the trigger 60 sets the signal of the logical unit (fig.5d), which arrives at the inverting input of the element 55 and prohibits its triggering, as a result of which only the first pulse of the first control voltage (Fig. 26) passes through the element 55 clock

and

ten

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generator 5. Furthermore, from the pulse voltage (fig. 2b), the counter 57 begins to fill up through the switch 54.

After filling the counter 57, a logical unit is established at its direct output, under the action of which a single-oscillator 58 is triggered and forms at its output a pulse (fig 5g), which enters the second input of the OR element 35, and passes it, enters the single trigger input 43 and sets it to the one state, as a result of which the inverse output of the trigger 43 is set to a logical zero. (Fig. 56), under the action of which the key 53 opens, the back front of the sawtooth voltage is formed (Fig. 5e).

At the same time, the pulse (Fig. 5d), the OR 35 element passed, is fed to the input of the zero setting of the counters 20, 30 and 57 and sets them to the zero state, sets the clock generator 5 to the initial state, goes to the control inputs of the keys 45 and 52, which for the duration of the specified pulse closes and discharges the capacitors of the storage elements 4 and 7. Pass through the elements OR 51 and 59, the pulse arrives at the control inputs of the keys 13 and 17, which operate for the duration of the action of the specified pulse and discharge RC capacitors chains 14 and 18. Chrome Moreover, the pulse (fig.5g) from the output of the one-shot 58 is fed to the first input of the element OR 42, and passed to the single input of the trigger 60, which is triggered, as a result of which its inverse output is set to a logical zero (fig.5d), enters the inverting input element 55 and does not affect its operation. Thus, the circuit elements of the imaging unit are returned to the initial state, and from the next cycle of operation of the clock generator 5, the formation of the next sawtooth voltage begins. (Fig.5e).

To adjust the amplitude, the sawtooth voltage changes the number of bits of the counter 57.

When forming trapezoidal-triangular, trapezoidal and sawtooth stresses, the device can be visually performed.

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total control. In this case, the periodic extinction of the display element 44 coincides with the moment of the beginning of the formation of the indicated voltages, and the moment of switching on coincides with the moment of the end of the formation of the output voltage on the output bus 64 of the device. In the initial state of the circuit element 44 is also included.

The proposed device, in comparison with the prototype, provides not only the formation of a symmetrical triangular voltage, but also ensures the formation of a highly stable signal of a trapezoidal-triangular shape, trapezoidal voltage and a sawtooth voltage. In addition, the generated voltages are characterized by high stability, since their parameters are determined by the total instability of the transfer coefficients of the adders and matching amplifiers of storage elements. When using a high-precision resistor in the trapezoidal-triangular voltage shaper voltage, the total instability of the transfer coefficients, not exceeding 1%, is easily achieved. At the same time, the temporary instability of the circuit parameters, due to the temporal instability and the capacitance capacitance value, is eliminated, which makes it possible to increase the time stability by more than a order of magnitude.

ness l.

output signal of the invention formula

A special waveform shaper containing the first and second RC circuits, the inputs of which are combined and connected to the inputs of the first and second input keys, and the outputs are connected respectively via the first and second keys to the common bus, the first adder, the first and second memory elements, the first and second output keys, the inputs of which are connected, respectively, with the outputs of the first and second storage elements, and the outputs are connected to the first input of the first adder, the second input of which is connected to the output of the first input key, t This input is connected to the output of the second input key, and the output is connected to the inputs of the first and second storage elements, the first and second 10

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the third, the fourth, the fifth and the sixth keys, the first and second pulse counters, the first to the third elements are NOT, the first and second elements are AND, the first and second elements are OR, the input voltage source, the clock generator, the second adder and from the first to the sixth BANNER elements, the direct input of the first BANNER element is connected to the first output of the clock generator, with the direct inputs of the second and third BANNER elements, with the first input of the first And element, with the counting input of the first pulse counter and with the control the outputs of the first output key and the second storage element, the output with the control input of the second input key, and the inverting input of the first element BANGE is connected to the inverse output of the first pulse counter, the installation input to the zero state of which is connected to the installation input to zero, the second pulse counter, and the direct output - with the inverting inputs of the second and third elements BANKS, through the first element NOT - with - the direct input of the fourth element BANNERS, through the second element NOT - with the inverting input The fifth blocking element BANKS, as well as connected to the second input of the first element I, the output of which is connected to the control input of the third key and the first input of the first element OR, the second input of which is connected to the output of the fourth element BAN, and the output to the control input of the fourth a key whose input is connected to the output of the second RC circuit and through the first limiting resistor and the third key connected in series to the common bus, the first and second inputs of the second adder are connected to the outputs of the fifth and fourth keys However, the third input is connected to the output of the first storage element, the fourth input to the output of the second storage element, the output to the first output bus, and the input of the fifth key is connected to the output of the first RC circuit and connected in series to the second limiting resistor and The sixth key is with a common shi-. and the control input is with the output of the second OR element, the first input of which is connected to the third output30

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The second element is NOT; the second input is with the output of the fifth BANNER element, the direct input of which is connected to the control input of the sixth key and the output of the second element AND, the first input of which is connected to the input of the third element NOT, with the inverting inputs of the fourth and sixth elements and with the direct output of the second pulse counter, the second input with the direct input of the sixth BANGE element, with the counting input of the second pulse counter, with the second output of the clock generator and with the control inputs of the second output key and the first memory element, the output of the second element BANGE is connected to the control input of the first input key, and also containing the initial state bus, characterized in that, in order to expand its functionality, the first and fifth switches, the third element AND , third through fifth pulse counters, first and second triggers, indication element, first through fourth one-shot, third through seventh elements OR, seventh, eighth and ninth keys, third limiting resistor, and seventh and | eighth BANKS, the direct input of the seventh BANGE element is connected to the second clock generator output, the inverting input to the inverted output of the first pulse counter, and the output through the first switch is connected to the counting input of the third pulse counter, the forward output of which is connected to the first the input of the third element And, the second input of which is connected to the direct output of the fourth pulse counter and through the first one vibrator to the first input of the third OR element, and the output through the second one vibrator is connected to the first input ohm fourth element OR, the second input of which is connected to the first input of the fifth element OR and to the output of the third one-shot, the third

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the input is with the second input of the fifth OR element and the installation bus of the initial state, and the output is with the installation inputs to the zero state of the second, third, fourth and fifth pulse counters, with the first inputs of the sixth and seventh OR elements, with control inputs of the clock generator, the seventh and eighth keys and with a single input of the first trigger, the zero input of which is connected to the output of the third OR element, the direct output - with the input of the display element,% inverse output - with the control input of the ninth key and fourth ode Ovibrator - with zero input of the second trigger, a single input of which is connected to the output of the fifth OR element, and an inverse output - with an inverting input of the eighth BANNER element, the output of which is connected to the second input of the third OR Element, and the first input through the second switch is connected to the first a clock generator output which is connected via a third switch to the counting input of the fourth pulse counter, and through a fourth switch to the counting input of the fifth pulse counter, the direct output of which is connected to the input the third one-shot, while the input voltage source through the fifth switch is connected to the inputs of the first and second input keys, the second input of the sixth element OR is connected to the output of the third element BAN, and the output is connected to the control input of the second key, the second input of the seventh element OR is connected with the output of the sixth element BAN, and the output with the control input of the first key. cha, moreover, the seventh and eighth keys are connected respectively parallel to the capacitors of the first and second storage elements, and the output of the second adder is connected through the third limiting resistor and the ninth key in series with the second output bus.

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FIGAfig 5

Claims (1)

The claims _Λ 40 A special form of signal generator containing the first and second RC circuits, the inputs of which are combined and connected to the inputs of the first and second input keys, and the outputs are connected through the first and second keys to the common bus, the first adder, the first and second memory elements, the first and the second output keys, the inputs of which are connected respectively to the outputs of the first and second storage elements, and the outputs are connected to the first input of the first adder, the second input of which is connected to the output of the first input key, the third One is connected to the $ 5 output of the second input key, and the output is connected to the inputs of the first and second storage elements, the first and second limiting resistors, the third, fourth, fifth and sixth switches, the first and second pulse counters, from the first to the third elements NOT, the first and second AND elements, the first and second OR elements, the input voltage source, the clock generator, the second adder and the first to the sixth elements BAN, the direct input of the first BAN element is connected to the first output of the clock generator,, with the direct inputs of the second and of the third element is PROHIBITED, with the first input of the first element AND, with the counting input of the first pulse counter and with the control inputs of the first output key and the second memory element, the output is with the control input of the second input key, and the inverting input of the first element is FORBID connected to the inverse output of the first counter pulses, the input of the installation in the zero state of which is connected to the input of the installation in the zero domain of the second pulse counter, and the direct output with the inverting inputs of the second and third elements ET, through the first element is NOT - with the direct input of the fourth element is FORBID, through the second element is NOT - with the inverting input of the fifth element is FORBID, and also connected to the second input of the first element AND, the output of which is connected to the control input of the third key and the first input of the first element OR, the second input of which is connected to the output of the fourth BAN element, and the output - to the control input of the fourth key, the input of which is connected to the output of the second RC circuit and through the first terminating resistor and the third key connected in series - with a common bus, the first and second inputs of the second adder are connected to the outputs of the fifth and fourth keys, respectively, the third input is connected to the output of the first storage element, the fourth input is connected to the output of the second storage element, the output is connected to the first output bus, while the input of the fifth key is connected with the output of the first RC circuit and through the second limiting resistor and the sixth key connected in series with the common bus, and the control input with the output of the second OR element, the first input of which is connected to the output of the third element NOT, the second input is with the output of the fifth element BAN, the direct input of which is connected to the control input of the sixth key and with the output of the second element AND, the first input of which is connected with the input of the third element NOT, with the inverting inputs of the fourth and sixth elements BAN and with the direct output of the second pulse counter, the second input - with the direct input of the sixth element is FORBID, with the counting input of the second pulse counter, with the second output of the clock generator and with the control inputs of the second output key and the first storage element, etc. than the output of the second BAN element is connected to the control input of the first input key, as well as containing the initial state setting bus, characterized in that, in order to expand the functionality, the first to fifth switches, the third element And, the third to fifth counters are introduced into it pulses, the first and second triggers, an indication element, from the first to the fourth one-shot, from the third to the seventh elements OR, the seventh, eighth and ninth keys, the third limiting resistor and the seventh and | eighth elements are FORBID, the direct input of the seventh element is FORBID connected to the second output of the clock generator, the inverting input is connected to the inverse output of the first pulse counter, and the output through the first switch is connected to the counting input g of the third pulse counter, the direct output of which is connected to the first input of the third element And, the second input which is connected to the direct output of the fourth pulse counter and through the first one-shot to the first input of the third element OR, and the output through the second one-shot is connected to the first input of the fourth element and OR, the second input of which is connected to the first input of the fifth OR element and to the output of the third one-shot, the third input - to the second input of the fifth OR element and to the initial state bus, and the output - to the zero, second, third, fourth and fifth pulse counters, with the first inputs of the sixth and seventh OR elements, with control inputs of a clock generator, the seventh and eighth keys and with a single input of the first trigger .., the zero input of which is connected to the output of the third OR element, directly the th output is with the input of the indication element, the inverse output is with the control input of the ninth key and through the fourth one-shot with the zero input of the second trigger, the single input of which is connected to the output of the fifth OR element, and the inverse output with the inverting input of the eighth element BAN, output which is connected to the second input of the third. OR element, and the direct input through the second switch is connected to the first output of the clock generator, which through the third switch is connected to the counting input of the fourth pulse counter, and through the fourth switch to the counting input of the fifth pulse counter, the direct output of which is connected to the input of the third one-shot, the input voltage source through the fifth switch is connected to the inputs of the first and second input keys, the second input of the sixth element OR is connected to the output of the third element is FORBID, and the output is from the control the main input of the second key, the second input of the seventh OR element is connected to the output of the sixth element is FORBID, and the output is with the control input of the first key. ca, and the seventh and eighth keys are connected respectively parallel to the capacitors of the first and second storage elements, and the output of the second adder is connected in series through the third limiting resistor and the ninth key to the second output bus.