SU1370740A1 - Shaper of triangular voltage - Google Patents

Abstract

The invention relates to a pulse technique and serves to expand the functionality of the device. The driver contains an input key I, a source 2 of input voltage, memory elements 3 and 6, a clock generator 4, adders 5 and 14, output keys 7 and 8, keys 9 and 10, RC circuits 11 and 12. Keys 13 are entered into the device , 15 and 34 elements BANKS 16,18,19,23 and 27, input key 17, elements AND 20 and 28, counters 21 and 29 pulses, elements NOT 22, 30 and 32, elements OR 24 and 31 and limiting resistors 26 and 35. Due to this, it becomes possible to form a voltage of a symmetric triangular shape with a high stability of amplitude-time parameters, since non-stable the output voltage is determined by the total instability of the transfer coefficients of the adders 5 and 14 of the matching amplifiers of the storage elements. 2 Il. $ (L

Description

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about 1

Fig

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The invention relates to the pulsed technology and can be applied in automation devices.

The purpose of the invention is to expand the functionality of the device by ensuring the formation of a symmetric triangular voltage.

Figure 1 shows the block diagram of the device; Fig. 2 shows timing diagrams explaining the operation of the device.

The device contains the first input key 1, the input voltage source 2, the storage element 3, the clock generator 4, the adder 5, the additional storage element 6, the first and second output keys 7 and 8, the first and second keys 9 and 10, the first and second RC- circuit 11, 12, the third key 13, the additional adder 14, the fourth key 15, the first element 16 BANKS, the second input key 17, the second and third elements 18 and 19 BANNER the first element 20 AND, the first counter 21 pulses, the first element 22 NOT, the fourth element 23 BANKS, the first element 24 OR, the fifth key 25, the first positive resistor 26, fifth element 27 BANKS, second element 28 AND, second counter 29 pulses, second element 30 NOT, second element 31 OR, third element 32 NOT, sixth element 33 BAN, sixth switch 34, second limiting resistor 35, bus 36 setting the initial state of the device, the output bus 37. The input of the first input key 1 is connected to the source 2. The inputs of the first and second output keys 7 and 8 are connected to the outputs of the storage and auxiliary storage elements 3 and 6, respectively, the outputs are connected to the first input of the adder 3 second the stroke of which is connected to the output of the first input key 1, and the output is connected to the inputs of the storage and additional storage elements 3 and 6. The control inputs of the first output key 7 and the additional storage element 6 are connected to the first output of the clock generator 4, the second output of which is connected to the control the main inputs of the second output key 8 and the storage element 3. The first and second keys 9 and 10 are connected in parallel to the capacitors of the first and second RC circuits 11 and

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12, the inputs of which are connected to the output of source 2. The output of the first RC circuit 11 via the fifth key 25 is connected to the first input of the additional adder 14, the second input of which is connected via the fourth key 15 to the output of the second RC circuit 12, the third input to the output memory ele

3, the fourth input is with the output of the additional storage element 6. The output of the first element 16 is connected to the control input of the second input key 17, the first input is from

the first output of the generator 4 and the first inputs of the second and third elements 18, 19 and the first input of the first element And 20. The second inverting input element 16 is connected to

the inverse output of the first counter 21, the counting input of which is connected to the first output of the generator 4, and the direct output to the second inverting inputs of the elements 18 and 19, to the second input of the And 20 element and through the first element NOT 22 to the first input of the fourth element 23, the output of which is connected to the second input of the first element OR 24, the output of which is connected to the control input of the fourth key 15, and the first input to the output of the element AND 20 and to the control input of the third key 13, which through the limiting resistor 26 is connected to the output of the second RC -ts pi 12. The control input of the first switch 9 connected to the output of the sixth member 33, a first input coupled to the second output of the clock generator 4,

with the second input of the second element And 28 and with the counting input of the second counter 29, the second inverting input - with the direct output of the second counter 29, with the first input of the element And 28, with

the second inverting input element 23 and through the third element NOT 32 to the first input of the second element OR 31, the output of which is connected to the control input of the fifth key 25. The input

the second element HE 30 is connected to

the direct output of the first counter 21, and the output to the second inverting input of the fifth element 27, the output of which is connected to the second input of the second IPI element 31, and the first input to the output of the second element And 28 and to the control input of the sixth key 34, which through the second limiting resistor 35 is connected to the output of the first RC circuit 11. The outputs of the second and third elements 18 and 19 are connected respectively to the control inputs of the first input key 1 and the second key 10, and the set inputs to the first and second counters 21 and 29 are connected with bus 36.

The device works as follows.

The clock generator 4 forms two pulsed voltages that are shifted relative to each other (Fig. 2a, b).

The impulse voltage (Fig. 2p) controls the operation of the key 7, the key of the additional storage element 6, through the prohibitory elements 16, 18 and 19, the operation of the keys 17.1 and 10, respectively, through the element 20, the key 13, and through the elements 20 AND OR 24 is the key 15. The pulse voltage (FIG. 2) controls the operation of the key 8, the key of the storage element 3, through the BANNER element 33, the operation of the key 9, through the AND 28 element - the key 34, and through the sequence of AND 28 elements, the BAN 27 and OR 31 - key 25.

In the presence of positive pulses at the outputs of the clock generator 4, the keys are closed, and in the absence of pulses they open.

The adder 5 for each input has a single transmission coefficient.

RC capacitors 1I and 12 are discharged before switching on the device. The counters 21 and 29 are set to the zero state via the bus 36, as a result of which the inverse output of the counter 21 contains a logical unit signal, which arrives at the inverting input of the BAN 16 element and prohibits it from running. The direct output of the counter 21 is set to a logical zero signal, which is fed to the inverting inputs of the BANKS 18 and 19 elements and does not affect their operation, which ensures the passage of pulses (fig.2y) to the control inputs of keys 1 and 10, and through the element NOT 22, this signal in the form of a logical unit is fed to the input of the element BAN 23, which triggers and passes the signal of the logical unit to the second input of the element OR 24, since the inverting input of the BAN 23 is present a signal of the logical zero from the direct output counting Single 29. After passing through the FPI element 24, a logic signal

,

five

ten

20

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units enters the control input of the switch 15, which triggers and connects the output of the RC circuit 12 to the second input of the adder 14.

The logic zero signal from the output of the counter 29 also enters the inverting input of the BAN 33 element and does not affect its triggering, which ensures the passage of pulses (Fig. 2 (5) to the control input of the key 9, and passes through the HE element 32, enters as a logical unit to the first input of the element OR 31. From the output of the element OR 31, the signal of the logical unit arrives at the control input of the key 25, which triggers and connects the code of the RC circuit I1 to the first input of the adder 14.

Upon receipt of the first control pulse (Fig. 2), the keys 1.7 and the key of the storage element 6 are closed, and the pulse itself is recorded in the counter 21. The output of the adder 5 25 sets the voltage U. The capacitor of the storage element 6 is then output through a small output impedance adder 5 is charged before the voltage U. The parameters of the circuit are chosen so that the ratios are fulfilled

R, - C, (1)

RBX-C (2)

where R. is the output impedance of the adder 5;

capacitor capacitance in storage elements 3 and 6; control pulse duration;

input impedance matching amplifier storage elements.

When inequality (I) is fulfilled, the voltage to which the end of the current is charged

35

40

With the R .X capacitor, does not depend on the change in the value of its capacitance, and when inequality (2) is fulfilled, the voltage remains unchanged for a time when the key of the storage element is disconnected.

Thus, during the first period of the control pulses, the voltage at the output of the storage element 6 remains unchanged and equal to

and (figure 2 I.

Upon receipt of the second control pulse (Fig. 2-6), the key 8 and the key of the storage element 3 are closed, and the keys 1, 7 and the key of the storage element

51370740

element 6 is opened and the impulse itself

n x

entered into the counter 29. The voltage equal to and, from the output of the storage element 6, through the key 8 is fed to the input of the adder 5, the capacitor of the storage element 3 is charged to the voltage U. The voltage at the output of the storage element 3 is equal to and remains unchanged during the follow-up period of the control pulses (Figure 2d),

Next, the keys 1, 7 and the key of the storage element 6 are closed. At the same time, the output of the adder 5 sets a voltage equal to 2U, since the voltage equal to and is applied to the first and second inputs of the adder via the keys 1 and 7. The voltage from the output of the adder is recorded by the memory element 6, at the output of the matching amplifier of which a voltage of 2U is set (FIG. 2b). During the next clock cycle, this voltage is again written back to the storage element 3 (Fig. 2d). Further, the processes are repeated with period 2. As a result, stepwise voltages are generated at the output of the storage elements 3 and 6, shifted by time 1, and counters 21 and 29 are filled.

The step voltages (Figures 2, 8, and -z) from the outputs of the storage elements 3 and 6 are fed to the inputs of the additional adder 14. When these voltages are combined, the new step voltage is formed on the adder 14

a radiation whose steepness is twice as large as the steepness of the components of the stresses (figure 2 and).

In addition, with the periodic closure of the keys 9 and 10 under the action of the control pulses of the clock generator 4 on the capacitors of the RC circuits

35 pulses (Fig. 2 l) enter the control input of the key 17, and the control input of the key 1 receives the level of logical zero.

In addition, the logical unit

 from the output of the counter 21, having passed through the element NOT 22, in the form of a logical zero signal goes through the elements BANGE 23 and OR 24 to the control input of the key 15, which once 1 1 and 12 are formed sawtooth-like turns off and turns off the output of the RC circuit

yarns (Fig. 2e,.) with amplitude U. For correct operation of the circuit, the parameters of the additional adder 14. selected so that the ratios are fulfilled

to, and, to, - and

to, .and to,

and.

K, K - transfer coefficients of the adder 14 through the corresponding inputs;

and - input voltage amplitude;

Ujj is the voltage amplitude up to which the capacitors of the RC circuits are charged during time T. The RC time constant was selected so that only the initial portion of the capacitor charge exponent was used and the voltage at the circuit outputs was linear.

In this case, when summing the step voltage (Fig.) With sawtooth voltage (Fig. 2d, "supplied respectively to the first and second inputs of the adder 14, a linearly increasing voltage is obtained (Fig. 25) coming from the output of the additional adder 14 to the exit pitch 37.

After arriving at the entrance of the count

21 pulses, where n is the number of bits of counter 21, a logical unit appears at the forward output of counter 21, which enters the inverting inputs of prohibitors 18 and 19 and prohibits their triggering, and arriving at the second input

Element And 20, prepares it for work. Inverse output

 The counter 21 is set to a logical zero signal, which is fed to the inverting input of the BAN 16 element and does not affect its operation. Starting from this moment, the 35 pulses (Fig. 2 l) arrive at the control input of the key 17, and the control input of the key 1 receives the level of logical zero.

In addition, the logical unit

 from the output of the counter 21, having passed through the element NOT 22, in the form of a logical zero signal goes through the elements BANNER 23 and OR 24 to the control input of the key 15, which breaks and turns off the output of the RC circuit

0

five

12 from the second input of the adder 14. After the input of the counter 2 ch 29 t-pulses (width

counters 21 and 29 are the same) a logical unit appears at the forward output of counter 29, which arrives at the second input of the prohibition element 33 and prohibits its operation and also enters the first input of the element 28 and prepares its operation and passes through the element 32 this signal as a logical

zero through the OR element 31 is fed to the control input of the key 25, which opens and turns off the output of the RC circuit 11 from the first input of the adder 14,

The output of the switch 17 is connected to the inverting input of the amplifier included in the adder 5, as a result, after the pulses are sent to the counters 21 and 29 during each voltage stroke on the storage capacitors of the storage elements 6 and 3, they decrease by U value (Fig. 2c, d ) A falling portion of the step voltage is formed at the output of each of the storage elements 6 and 3 and at the output of the adder 5 (Fig. 21). At the same time, each time a pulse arrives (Fig. 2a), the first input of the And 20 element triggers the key 13, since the second input of the And 20 element contains the signal of the logical unit, the direct output of the counter 21. In addition to

Yes, these chains (Fig.21g). As a result, when summing the step voltage (Fig. 2) with sawtooth

i voltages (fig. 2k,), supplied respectively to the second and first input of the adder 14, result in a falling portion of the linearly varying voltage (fig. 2o).

 O After the passage of 2 pulses to the meters 21 and 29, the voltages on the capacitors of the storage elements 6 and 3 are reduced to zero, and the meters 21 and 29 are set to the original zero state again. At the same time, when the counter 21 is set to the zero state and the logical unit appears at the output of the element NOT 22, the key 15 does not work, so

20 at this time from the output of the counter 29 to the inverting input of the element ZALRET 23 a signal of a logical unit is received and prohibits its activation. In addition, the signal is logical30

Moreover, through key OR 24 running zero from the output of counter 21, the key 15 passes, connecting for a time the NO 30 element in the form of a logic pulse (Fig. 2a) to the output of RC circuit I2 via the second input of adder 14 As a result, the discharge voltage of the capacitor of the RC circuit 12 is fed to the input of the adder 14 (FIG. 2h).

Similarly, when pulses (Fig. 26) are received at the second input of element 28, key 34 is triggered, since a signal of a logical pulse is present at the first input by the element state after passing through 2 -1-ta and 28. In this case, the capacitor of the RC circuit 1I is discharged, and the capacitor of the RC circuit 12 is charged, but the voltage from their outputs does not flow to the inputs of the adder 14, the output of which remains for a time zero voltage level. After being set to zero, the unit enters the inverting input of the element BANGE 27 and prohibits it from running.

As a result, the pulse that passed to counter 29 and set it to the zero state, passes to key 34 and is not passed to key 25, which remains in the open

40

The new state of the counter 29 circuit returns to its original state for

unit from the direct output of the counter 29. At the same time, the signal from the logical one) from the output of the element And 28 is fed to the input of the element BANGE 27, which triggers and passes the signal of the logical unit to the second input of the element OR 31, since the inverting input of the BAN element 27, a logical zero is present with an output that the output of the RC element NO is 30 and the voltage 12 does not affect its circuit. Under the action of logic and ", but at the moment when the first unit emerges from the output of the element OR 31 pulse (Fig. 2a), the key 25 starts up and the output time of the pulse RC-50 is activated during the symmetric voltage cycle the bit of this circuit, which pi 11 to the first input of the adder 14 does not affect the operation of the circuit (Fig. 2k).

Upon subsequent receipt of clock pulses, the processes are repeated in a similar way, 55 resulting in the generation of symmetric step voltages at the outputs of the storage elements 6 and 3, and a symmetrical triangle at the output of the adder 14 (Fig. 2).

The parameters of the constant discharge time through the switch 13 and the resistor 26 of the RC circuit 12 and through the switch 34 and the resistor 35 of the RC circuit 11 are chosen so that the voltage at the outputs of the circuits is linear and symmetrical with the voltage of the

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Yes, these chains (Fig.21g). As a result, when summing the step voltage (Fig. 2) with sawtooth

i voltages (fig. 2k,), supplied respectively to the second and first input of the adder 14, result in a falling portion of the linearly varying voltage (fig. 2o).

 O After the passage of 2 pulses to the meters 21 and 29, the voltages on the capacitors of the storage elements 6 and 3 are reduced to zero, and the meters 21 and 29 are set to the original zero state again. At the same time, when the counter 21 is set to the zero state and the logical unit appears at the output of the element NOT 22, the key 15 does not work, so

20 at this time from the output of the counter 29 to the inverting input of the element ZALRET 23 a signal of a logical unit is received and prohibits its activation. In addition, the logical zero signal from the output of the counter 21, passed through the element 30 in the form of logic

0

 first zero from the output of counter 21, having passed through the element NOT 30 in the form of logical

Volume 5 after passing the 2 -1st pulse. In this case, the capacitor of the RC circuit 1I is discharged, and the capacitor of the RC circuit 12 is charged, but the voltage from their outputs does not flow to the inputs of the adder 14, the output of which remains for a time zero voltage level. After being set to zero, the unit enters the inverting input of the element BANGE 27 and prohibits it from running.

As a result, the pulse that passed to counter 29 and set it to the zero state, passes to key 34 and is not passed to key 25, which remains in the open

35

40

50

The new state of the counter 29 circuit returns to its original state for

except that at the output of the RC circuit 12 there is a voltage of magnitude and „, but at the moment of the appearance of the first pulse (fig. 2a) of the formation of a new symmetric voltage cycle, this circuit is discharged, which does not affect the operation of the circuit (fig.2k).

voltage. When an LED indicator is connected to the inverse output of the counter 29, it is possible to visually monitor the operation of the device,.

The device allows to form voltages of symmetric triangular shape with high stability of amplitude-time parameters, since the instability of the output voltage is determined by the total instability of the transfer coefficients of adders and matching amplifiers of storage elements. When using a high-precision resistor in the proposed circuit, the total transfer coefficient instability is easily achievable, not exceeding 1%. In this case, the temporal instability of the circuit parameters, due to the temporal instability of the capacitor capacitance, is eliminated, which makes it possible to increase the temporal stability of the output signal parameters of the driver and to ensure the formation of a symmetrical triangular voltage for more than an order of magnitude.

Claims (1)

Invention Formula A triangular voltage driver containing the first and second KS circuits, the inputs of which are connected to the input voltage source, and the first and second keys, the first input key, the adder, the memory and additional memory, are connected in parallel to their outputs s 7074010 with the control input of the first output key and the control input of the additional storage element, the second output with the control input of the second output key and the control input of the storage element, characterized in that, in order to expand the functional capabilities, the first and second limiting resistors, third, fourth, fifth and sixth keys, first to second elements BANKS, first and second counters im15 pulses, first to third elements NOT, first and second elements AND, first and second elements s OR and the second input key, the input of which is connected to the input source 20, the output - with the third input sum5 the torus, and the control input - with the output of the first element BANGE, the input of which is connected to the first output of the clock generator, with the inputs of the second 0 and the third BANNER element and with the first input of the first element I, the inverting input is connected to the inverse output of the first pulse counter, the counting input of which is connected to the first output of the clock generator, the setting input to the zero state - to the input setting to the zero state BTQporo of the counter and bus installation of the initial state of the device, 5 and direct output - with the inverting inputs of the second and third elements of the BAN, through the first element NOT - with the input of the fourth element BAN, through the second element NOT - with the inver elements, the first and second output - the input of the fifth element BANGE, and is also connected to the second input of the first element AND, the output of which is connected to the control input of the third key and the first input of the first The keys, the inputs of which are connected respectively to the outputs of the storage and additional storage elements, the outputs are connected to the first input of the adder, the second input of which through the first input key is connected to the input voltage source, and the output is connected to the inputs of the storage and additional storage elements, an additional adder, having the first, second, third and fourth inputs, the third input of which is connected to the output of the storage element, the fourth input - to the output of the additional storage e the output is connected to the output bus, as well as the clock generator, the first output of which is connected the second input of the first element BAN, and also connected to the second input of the first element AND, the output of which is connected to the control input of the third key and the first input of the first element OR, the second input of which is connected to the output of the fourth element BAN, and the output to the control input the fourth key, the input of which is connected to the output of the second RC circuits and through series-connected first limiting resistor and third key - with zero thickness, output - with the second input of the additional adder, the first input which is connected to the output of the fifth key, the input of which is connected to the output of the first RC circuit and through the second limiting resistor and the sixth switch connected in series to the zero bus, and the control input to the output of the second OR element, the first input of which is connected to the output of the third the element is NOT, the second input is with the output of the fifth element BANGE, the input of which is connected to the control input of the sixth key and the output the second element And, the first input of the KOTO-IQ of the prohibition is connected to the control connected to the inverting input of the second key, and the output of the sixth BAN element, the second input BAN element connected to the control input of the six BAN element, the first input of the first key, the second clock generator output but ppppppppppppppppppp ppppppppppppppppppp / and the counting input of the second pulse counter, the direct output of which is connected to the input of the third element NOT and the inverting inputs of the fourth and sixth elements of the BAN, the output of the second element BANNING connected to the control input of the first b key, the output of the third ele