SU1529231A1 - Information input device - Google Patents

Abstract

The invention relates to computing technology and can be used in multiple measurement information systems for express analysis, preparation and input to a computer of experimental data in scientific research. The aim of the invention is to simplify the device and increase its noise immunity. The device contains a control unit, an interface unit, a mode setter, a write control unit, a pulse synchronization recovery unit, the first driver from the first to the ninth triggers, a pulse generator, a counter, the first decoder, a second counter, the first memory block, the second decoder, the first a register, a second memory block, a second register, a second signal conditioner, a second and third counters, a first switch, a code comparator, a code receiver, a third register, a fourth register, and a second switch. The device allows to increase the noise immunity of the input information due to the recovery of the missing sync pulses. 13 il.

Description

The invention relates to computing and can be used in multichannel measurement information systems for express analysis, preparation and input to a computer of experimental data in scientific research.

The purpose of the invention is to simplify the device and increase its noise immunity.

1 shows a block diagram of a device for inputting information; Fig. 2 is an electrical diagram of a mode knob; Fig. 3 is an electrical diagram of a code comparator; 4 is an electrical diagram of a pulse generator; FIG. 3 is an electrical circuit of the conjugation block; Fig. 6 is an electrical circuit of the second driver; Fig. 7 is an electrical diagram of the first shaper; FIG. 8 is a block diagram of a clock recovery unit; Fig. 9 is an electrical circuit of the generator; Fig. 10 is a block diagram of the control block after the record; figure 11 is a block diagram of the receiver code; 12 is the electrical circuit of the one-shot; in fig. 13 - page of the control circuit diagram.

The device (Fig. 1) contains the control unit 1, the interface unit 2, the 3s control unit, the recording control unit 4, b | n: ok 5 recovery of the sync pulse, the first driver 6 signals the first 7, the second 8 and the third 9 trigger generator 10 pulses first

Atchik 11, first decoder 12, second counter 13 J quarter trigger 14, first memory block 15, fifth 16, sixth i7 and seventh 18 flip-flops, second decoder 19, eighth 20th and ninth

 the first register is 22, the memory block 23 of the S memory is the second register 4e the second driver 25 signals, 26 and the third 27 counters, the first

th switch 28, comparator 20 ko; 03 5 reception1-shk 30 kode third 31 and the fourth 32 registers and the second commutator 33.

In FIGS, the positions 34-160 denote the libi inputs of the blocks 5, which constitute the mouth | OYSTVO,

Unit 3 modes (figure 2) includes the first 161 and second 162 elements of the IE, the limiting element 163 in the resistor, the shunt element 164

in the form of a diode5, a switching element 65 in the form of a relay, an amplifying element | 16b 3 as a transistor, and the first 57 l second 168 elements of NAND.

The comparator 29 codes (fig.Z) form the element NOT i 69 ,. the element WORKING-SAFETY 170 and the element AND 7. I The pulse generator 10 (FIG. 4) contains the AND-NE element 172, the load element 173 in the vice time resistor - the guessing element 174 in the form of a capacitor and the first 175 and second 176 elements NOT,

The interface block 2 (FIG. 5) forms the first 177, the second 178, and the third 179 dividing elements in the form of resistive jpOB, the restricting element 180

The code receiver 30 (Fig. 11) is the one-shot 233, the element is NOT the first 235 and the second is 236 trig the first 237 ,, the second 238, and the three elements that break 240 in the form of a capacitor, the naked element 241 in the form of a resistor, the AND-NE 242, the first the second 244 elements 2I-2ILI element AND-NOT 245, the third fourth 247 and the fifth 248 the fifth element AND-NOT 249, the registrant and the sixth 251 and seventh

50

| form of the diode, the amplifying element 181 in the form of a transistor and the load element triggers.

; ment 182 in the form of a resistor. Single vibrator 233 (Fig. 12)

 The second driver (FIG. 6) includes an AND-HE element 183 and a decoupling element 184 in the form of a diode,

The first driver 6 () contains a restrictive element 185 in

resistor shunt

: 186 in the form of a diode 5 switching element 187 in the form of a relay and amplifying

: element 188 in the form of a transistor.

; Block 5 recovery sync: pulses (Fig.8) includes the element And 189s register 190, the pulse generator 191, the first counter 192, the element

55

the trigger 253, the first 254 255 limiting resistor elements, decoupling the electric diode, the recharge 257 in the form of a capacitor, the first and the second 259 amplifying electric transistors, the first 26 pj 261 transition capacitor elements and the HE element

The control unit 1 (Fig. 13 shows the first element NOT 263, from the eighth elements AND 264-27 273 and the second 273 elements IL

RSHI-HE 193, second counter 194, first element NOT 1 95, first P 96 and second 197 triggers, first element 2K KLI-NOT 198, AND-NOT 199 element, second element II-OR-NOT 200, decoupling element 201 in the form the capacitor, the load element 202 in the form resis.tora, the second element is NOT 203 and the third counter 204.

The pulse generator 191 (FIG. 9) incorporates the first element HE 205, the first 206, the second 207, the third 208, and the fourth 209 the time specifying elements in the form of a resistor, capacitor, quartz, and resistor, and the second element HE 210.

The recording control block 4 (FIG. 10) constitutes the first 211 and second 212 triggers, the first 213, the second 214, the third 215, the fourth 216 and the fifth 217 And elements, the third trigger 218, the first 219 and the second 220 I-NOT elements, the fourth trigger 221, the third element AND-NOT 222, the sixth element AND 223, the fifth trigger 224, the seventh element AND 225, the first 226 and the second 227 elements HE-ilJIHj, the fourth element AND-HE 228, the element 2I-2, OR 229, the sixth trigger 230, the element is NOT-231 and the third element is NOT-SHI 232.

The code receiver 30 (Fig. 11) contains a single vibrator 233, a HE element 234, a first 235 and a second 236 triggers, a first 237, a second 238, and a third 239 elements, a decoupling element 240 in the form of a capacitor, a load element 241 in the form of a resistor, a fourth element AND-NO 242, first 243 and second 244 elements 2I-2LINE, fifth element AND-NOT 245, third 246, sharper 247 and fifth 248 triggers, fifth element AND-NOT 249, register 250, and also the sixth 251 and seventh 252

triggers.

0

Single Vibrator 233 (Fig.12)

five

includes trigger 253, first 254 and second. 255 limiting elements in the form of resistors, a decoupling element 256 in the form of a diode, a retaining element 257 in the form of a capacitor, a first 258 and a second 259 amplifying elements in the form of transistors, a first 260 and a second 261 transition elements in the form of capacitors, and a HE element 262,

The control unit 1 (Fig. 13) contains the first element NOT 263, the first through the eighth elements AND 264-271, the first 273 and the second 273 elements OR, and the action 10

25

element 274, with my elements OR 275-280 | the second element is NOT 281, from the tenth to the thirteenth elements AND 282-285, the ninth element OR 286, the fourteenth 287 and the fifteenth 288 elements AND, the tenth element OR 289, from the sixteenth to the eighteenth elements AND 290-292, the eleventh element SH 293, the nineteenth element of the element And 294 and the twelfth element of the NL 295,

Unit 3 mode in figure 2 works as follows.

The signal at input 58 controls the connection of the relay 165, through the contacts of which a voltage is applied, which determines the operating mode of the interface 2 block at input 56. In addition, the signal at input 58 is the control for the switch assembled on elements 167 and 168, which commutes the signal at input 57 to input 115 or to input 114.

The code comparator 29 of FIG. 3 contains four nodes consisting of elements 169 and 170 for comparing each of the four-bit code bits at inputs 123 and 124. The outputs of these nodes are connected in AND 171. The comparison signal is fed to input 73.

The pulse generator 10 of FIG. 4 generates oscillations only if the input 1 of the input 17 of the element 172 is given a signal 1.

The interfacing unit 2 of FIG. 5 is a signal level converter over inputs 52-55 to TTL levels. Input 56 receives a control signal.

A shaper 25 of FIG. 6 is matching for transmitting data to a computer. It contains twelve identical cascades.

Shaper 6 of FIG. 7 is a transistor switch, the load of which is relay 187 with executive contacts.

The sync pulse recovery unit 5 of FIG. 8 operates as follows. A series of channel sync pulses recorded on a magnetic tape is reproduced by a magnetic recorder and through the interface 2 enters the sync pulse recovery unit 5 on input 74. The control word on input 75, which sets the operation mode of block 5, is written to the eight-bit register 190 by a signal on input .77, eight-digit code from register output

1529231

the third of the eighth-190 is fed to the input of the counter 192,

thus setting the conversion factor. The conversion factor is calculated so that

thirty

40

45

50

55

Where

Th T

 pt

 SP

 gt

st

st

T h

P the period of the following pulses from the output of the counter 192; oscillation period of the pulse generator 191; conversion factor; Tj is the period of channel. Sync pulses; m - fixed coefficient

filling.

In the initial state, block 5 is driven by input signal 76.

The incoming channel sync pulse passes through logic element 198, differentiating the circuit 201, 202, inverter 203 and sets the trigger 197 to state 1, counter 194 to state O and counter 204 to the initial state.

The output signal of the trigger 197 permits the passage of the signal from the output of the counter 192 through the IS-NE element 199. From the output of the element 199, the signal of the counter 192 goes to the counting input of the counter 204. The output signal of the second discharge of the counter trigger 196 is set to the state O and its output signal prohibits the passage of the signal through element 198. The signal from the output of the third bit of the counter allows the signal to pass through element 198. This resolution is the beginning of the time interval during which block 5 waits for the arrival of a new channel channel pulse pulse. The incoming sync pulse re-installs the counters. 194 and 204 and the trigger 197 to the initial state, etc.

If the sync pulse does not arrive during the waiting period of the channel sync pulse, then at the end of the sleep interval, the output signal of the counter 204 forms its own sync pulse that passes through the element 200 and exits the block 5.

The output signal of the counter 204 enters the counting input of the counter 194. Upon hitting the channel sync pulses, the counter 194 overflows and the output signal sets the entire block 5 to its initial state;

ten

25

15 20

thirty

40

45

0

five

Where

Th T

 pt

 SP

 gt

st

st

T h

P the period of the following pulses from the output of the counter 192; oscillation period of the pulse generator 191; conversion factor; Tj is the period of channel. Sync pulses; m - fixed coefficient

filling.

In the initial state, block 5 is driven by input signal 76.

The incoming channel sync pulse passes through logic element 198, differentiating the circuit 201, 202, inverter 203 and sets the trigger 197 to state 1, counter 194 to state O and counter 204 to the initial state.

The output signal of the trigger 197 permits the passage of the signal from the output of the counter 192 through the IS-NE element 199. From the output of the element 199, the signal of the counter 192 is fed to the counting input of the counter 204. prohibits the passage of the signal through element 198. The signal from the output of the third bit of the counter allows the signal to pass through element 198. This resolution is the beginning of the time interval during which block 5 waits for the arrival of a new channel channel nhroimpulsa. The incoming sync pulse re-installs the counters. 194 and 204 and the trigger 197 to the initial state, etc.

If the sync pulse does not arrive during the waiting period of the channel sync pulse, then at the end of the sleep interval, the output signal of the counter 204 forms its own sync pulse that passes through the element 200 and exits the block 5.

The output signal of the counter 204 enters the counting input of the counter 194. Upon hitting the channel sync pulses, the counter 194 overflows and the output signal sets the entire block 5 to its initial state;

} | 1Recreating the formation of your own finchroimulsov,

Unit 5 continues to work only “(after the arrival of the next channel sync pulse from block 2 of the interface.: The pulse generator 191 in FIG. 9 is built using a quartz crystal; 5 okter and oscillates a fixed frequency.

The recording control unit 4 of FIG. G is a logical node that provides signals for writing and reading information in memory block 23.

The receiver 30 of the code in FIG. 11 works as follows, Sequence; the time code on input 131 enters the one-shot 233. The output signal of the one-shot 233 enters the input of the AND-NE element 237, on the second turn of which the sequence arrives: th time code. A single vibrator 233 is triggered by each clock pulse of the post-sampling time code. The pulse duration of the one-shot 233 lag is 5 such that the time stamp following the sync pulse appears at the output of element 237 and sets trigger state 235 to 236 to 1. The output signal of the forward or inverse trigger output 235 is dependent on state 10- The first bit of the control word of the element 238 I or 239 goes either to the right shift information input or to: left left shift information input; gistra 250. The output trigger j 236s passes through the differentiating circuit 240, 241, is fed to the input of the element 243, from the output of which passes to the input of the installation in the O register 250 and to the input of the installation in 1 of the trigger 247 Signal. element 245 enters the record entry of register 250 and records the signal either from element 238 or from input 132 to the first register register 250. Following the time stamp, the data bit of the sequential time code sets the trigger 235 to the appropriate state; whereupon the state of the trigger 235 is recorded in the first register register 250, and the information in it is shifted in the second category. Thus, all sixteen bits of the sequential time code are written to the register. After recording the sixteenth bit on you

five

G

five

0

five

0

five

during the register 250, a signal appears) (the signal recorded at the beginning of the time stamp), which, having passed through the element 244, sets the trigger 236 to the state O. Thus, the conversion of the sequential time code into the parallel switch is completed. The signal at input 147 in the presence of signal 1 from the output of the trigger 247 produces a signal that initializes the triggers 247 and 248. The signal at input 130 records the parallel time code in the register 250 at input 43, Triggers 246, 248, 251 and 252 are intended to synchronize the input of information into the computer.

The single-oscillator 233 of FIG. 12 is programmed with a signal pattern of the input 132. The signal pattern of the controls controls the transistor switches 258 and 259, which switch the capacitors 260 and 261. The signal of the serial time code is inputted 131.

The control unit 1 of FIG. 13 is a combinational logic node that performs logical functions.

The input device operates as follows.

Between two adjacent information input operations from the information source (multichannel magnetic code recorder) to the information receiver (computer), the setting is made for specific parameters of the input information by performing the following operations:

issuing from a computer and writing to the recovery unit 5 sync pulses the conversion factor Kn. The conversion factor is a number that satisfies the relation

14 T

SP

one

-SG

where frakT oscillator frequency 191;

f SP

T is the frequency and period of the channel clock pulses. The conversion factor comes from the EPM at input 134 to register 31 and is recorded in register 31 by a signal coming in via bus 133-From the output of register 3, the code of the conversion factor.

a characteristic feature of which is signal 1 in the most senior (zero) de register 31, enters block 5 and is recorded in block 5 in register 190 of the conversion factor by the signal at input 77;

output from the computer and writing to the register 31. The control word is output from the computer at input 134 following the code of the conversion factor and is recorded in register 31 by the signal at input 133. A characteristic sign of the control word is the presence of O in the senior (zero) bit data entry 134; from a computer;

I control read control word. The information from register 31 at input I60 is connected to the input of the CM3 of the torch of the rectifier, and is received in the computer at input 152 by a strobe signal at input 153.

Consider the purpose of each of the control word bits:

O - contains the sign of the control word;

1-6 is not used;

7 - the presence of 1 allows the operation of the sync pulse recovery unit 5,

if O is present, the sync pulse is transmitted to input 74 on the output of block 5 unchanged; I 8 and 9 - contain information for setting up the block 2 conjugation.

The signal O from bit 9 at input 58 enters the setpoint adjuster 3 modes. At the same time, at the input 102, the signal of setting the interface unit 2 to the mode of receiving signals of negative polarity appears. Signal 1 from bit 9 sets block 2 to receive positive polarity signals.

The signal 1 from bit 8 at input 58 enters the setting device 3 modes and, together with the signal at input 57, generates signals at inputs 113-1155 which allow recording information from the magnetic recorder through the interface 2 at input 112 to be written to register 22.

The signal O from bit 8 forms the inverse code of the reception register 22.

Bit 10 controls the conversion of a serial time code to parallel. For the sake of explanation, consider the structure of a sequential time code signal. This signal is a continuous sequence of pulses, the following

ten

five

0

five

0

five

0

five

0

five

at a frequency of 1 kHz, in which a serial code appears once a second between pulses. .Signal 1 at input 132 in bit 10 of the control word initiates in the code receiver 30 a serial code in parallel in such a way that the bit following the time stamp becomes the high bit of the code that receives the computer at output 152.

The signal O on input 132 in bit 10 of the control word allows the generation of a parallel code in which the bit following the time stamp becomes the lower digit of the code received by the computer on output 152.

The presence of the signal O in the 11th dec. Prohibits the conversion of a sequential time code into a parallel one.

12-1, 13th, 14th bit are used when changing the playback speed of the tape mechanism. magnetic recorder. The two-bit code of bits 12 and 13 of the control word over the bus 132 enters the code receiver 30 and controls the operation of the single-oscillator 233, which generates a signal with a duration corresponding to the speed of the tape recorder of the magnetic recorder.

The three-bit code of the control word bits at input 75 enters the sync pulse recovery unit 5, where it controls the operation of the counter 192, the frequency of the output signal of which should depend on the speed of the tape recorder of the magnetic recorder.

Bit 15 is used to control the operation of the tape drive mechanism. Record in block 15 of the memory of the table of one-digit codes of selector masks. Before recording, blocks 13, 18, 16, 14, and 21 are reset by signals at inputs 90, 104, 98, 91, and 110. Next, the writing algorithm is as follows: the table of selector mask codes, previously formed in computer RAM, is transmitted from The computer is bit-mapped at input 41 to control unit 1 and then to input 96 to trigger 16, where it is recorded with a signal from input 97. Then the output signal of trigger 16 to input 95 is transmitted to the information input of memory block 15. The address of the unit 15 is passed through the inputs 92 and 94 to the address of the memory cell.

eleven

IB which I need to record (in this case, the record starts with a zero address). The recording produces an | with a signal at input 93. After that, with a signal at input 89, the counter 13 increases its state by one and the next bit of information is recorded according to the described algorithm.

For the control table, the Q-tables of the one-digit selector codes from block 15 to the computer before reading start the counter 13 is reset to the initial state by a signal on input 90 (you must start reading from the zero address of block 15)

To record the readout of the block 15, trigger 21 is set to state 1 by a signal on input 111.

The read cycle begins with the output of a short-circuit computer signal at input 38.

20

35

The signal at input 38 generates a signal in the block 1 of the control unit, which sets the 1. trigger 9 with the signal at 25 input 87. The trigger 9 turns on the generator 10 with the signal at input 125. The pulse sequence of the generator enters the counter 11 at the input 126. Four-bit the counter code ZO ka 11 enters the decoder 12 via input 128. At the output of the decoder 2, with each pulse of the generator Yu, a corresponding unitary code is formed. The generator 10 generates sixteen pulses, and then stops, being switched on by input 125 by trigger signal 9, which is set to state O by input 86. Blocks 10-12 open the control unit, the commands of which are output signals of the decoder 12 The control automat generates sequentially scrupulous ad commands of AO-A16. The output signals d of the control unit on input 48 are fed to control unit 1, in which the read control signals are generated. The reading is performed according to the following algorithm. The information read from the zero cell on input 99 is transmitted to the trigger 17, where it is recorded by the signal on input 100. After this, the signals on inputs 49 and 48 of control block i in block 1 generate a signal on input 89, which redirects I

those. increases

per unit the address of the counter 13. The input signal 101 trigger 17 us152923112

It is forced into O. The output signal of the trigger 17 is fed through the input 50 to the control unit 1, where it generates a signal which, via the input 71, goes to the recording control unit 4 and, together with the signal from the input 63, generates a setting signal to 1 trigger 230 in the case when Signal 1 was read from the cell. The computer, analyzing the state of output 157, makes a decision on the cell status of block 15: if output 157 is in state 1, then this cell of memory block 15 contains 1. After analyzing the state of output 157 computer enters the signal at input 72, which in block 4 generates a signal On al installation latch 230. In the case where a cell of the memory unit 15 to read a signal O, l setting signal in the flip-flop 230 is not formed and the trigger 230 remains in state A.

When entering, the following functions are performed:

- control of the magnetic recorder tape drive mechanism. A sign of the inclusion of a tape drive mechanism is the presence of 1 in the 15th bit of the control word. The information contained in the 15th control word bit at input 78 enters shaper 6. If input 78 is in state 1, then transistor 188 is open and relay 187 closes the contact command of the tape drive with its contacts. outputs 158 and 159;

- input of information flow with damping and selection. The signal to start the input is to set trigger 7 to state 1 by input 80, which is formed in control block 1 from input 34 and 35. The output signal of trigger 7 on input 85 goes to information input 9 of the trigger, preparing the spr for installation at i

After switching on the tape mechanism, the magnetic recorder. The first sync pulse received at the input 54, having passed through block 2 and block 5 at input 74, enters control block 1 at input 42, where, together with the signal at input 49, generates a signal from. input 88, which sets trigger 1 to 1. Signal 1 from trigger code 9 to input 125 triggers an automatic control. Sig50

55

control unit, which is transmitted via control unit 1 on input 157 to unit 3 settings, and from there, depending on the selected mode, either on input 114 or input 115 to reception register 22, information from a magnetic recorder,. having passed through the input 52 through the interface 2, at the input 112 is recorded in the reception register 22. From register 22, information on input 136 is fed to the input of memory block 23. The damper is the part of the device, which includes blocks 4, 23, 24, 26-29. The counter 26 and the counter 27 are set to the initial zero state by a signal on inputs 116 and 118, which is formed in block 1 of the control from signals on inputs 47 and 48.

The output signals of blocks 26 and 27 via inputs 120 and 121, respectively, are fed to the input of switch 28, which is switched by a signal on input 122, coming from recording control unit 4, in which is generated by control signals A9 and All on inputs 59 and 61, respectively . In addition, the counter output signals

0

five

five

0

from the signals at inputs 49, 57 and 68 in the control unit 1, and is reset by a signal formed from the signals at the inputs 47 and 48 in the control unit I. After the information has been recorded in memory block 23, a signal on input 122 is connected to the address input of memory block 23 via switch 28, input 121 of counter 27 of the address of the link is connected, and information on input 138 is input to register 24. At this time, signals on inputs 68 and 69 B block 4, a signal is generated at input 117, which increases the state of counter 26 by one. By the coincidence of the signals at inputs 73, 68, and 69, in block 4, a signal is generated, which, at the installation input, sets state 1 to trigger 230 if from memory 15 there was signal I. Output The trigger signal 230 enters the computer at output 157. Analyzing the state of output 157, the computer outputs a signal at inputs 62 and 66, which in block 4 generates a signal at input 139, which records information from input 138 to register 24. From the output repist

kuv 26 and 27 at the inputs 123 and 124, respectively, Qa 24 information is received at the input

144 to the driver input 25. After that, the signals from the computer on inputs 60 and 66 form in block 4 a signal on inputs 119 and 154, which increases the state of the meter 27 by one and gates the driver 25, broadcast information from the input 144 to the computer on the output 155. Simultaneously, in block 4, a signal is generated from inputs 60 and 66 which, on the reset input, sets the ready trigger to state 230, preparing the device to receive the next information word from the magnetic recorder.

35

The main signal is fed to the input of the comparator 29 codes, and if the codes are equal, the inputs 1 and the input of the comparator 29 codes will receive a signal 1, which is fed to the input 73 of the block 4.

Thus, before receiving the first information word from the magnetic recorder, blocks 26 and 27 are in the initial state and output of block-20 is connected to the address input of memory 23 via input 137 via switch 28 via input 120. So, recorded in Register 22 enters input 136 into memory block 23. The signal at input 135, which is formed in block 1 of control from signals at inputs 48 and 50, is recorded in memory block 23, provided that the signal at input 50 is level 1. Signal at input 50 is generated by trigger 17 when from memory block 15, signal 1 is considered at input 99. The process of combining information is

45

50

144 to the driver input 25. After that, the signals from the computer on inputs 60 and 66 form in block 4 a signal on inputs 119 and 154, which increases the state of the meter 27 by one and gates the driver 25, broadcasts information from the input 144 to the computer on output 155 At the same time, in block 4, a signal is generated from the signals at inputs 60 and 66, which, at the reset input, sets the ready status trigger 230 to the state O, preparing the device to receive the next information word from the magnetic recorder.

The damping of information in the proposed device is caused by the features of the computer operation. A computer receives information and writes it into its RAM through a direct memory access channel (CELP). The CAPA perceives information incessantly, and in portions. The size of the portion is specified by the program. When the portion of reception is completed, the input of information is terminated until

from memory block 15, the control program will not reconfigure

KDPP on a new portion. The information received in the meantime should be preserved even as a control read, except that the counter 13 is redirected by a signal to be generated. To save information and

Q ra 24 information arrives at the entrance

35

45

0

144 to the driver input 25. After that, the signals from the computer on inputs 60 and 66 form in block 4 a signal on inputs 119 and 154, which increases the state of the meter 27 by one and gates the driver 25, broadcasts information from the input 144 to the computer on output 155 At the same time, in block 4, a signal is generated from the signals at inputs 60 and 66, which, at the reset input, sets the ready status trigger 230 to the state O, preparing the device to receive the next information word from the magnetic recorder.

The damping of information in the proposed device is caused by the features of the computer operation. A computer receives information and writes it into its RAM through a direct memory access channel (CELP). The CAPA perceives information incessantly, and in portions. The size of the portion is specified by the program. When the portion of reception is completed, the input of information is terminated until

 the control program will not reconfigure

Nits. To save information and

,

serves as a damper. Damping is as follows. If after writing to memory block 23 and setting trigger 230 in block 4-into state, 1 computer does not receive signals at inputs 62, 60 and 66, i.e. the signal is not generated at the input 119 to redirect counter 27, the code comparator 29 sets the state O at its output 73. With the arrival of a new information word, the state of counter 26 is increased by one, etc. until KDPP starts to accept information. In this state, the trigger 230 remains unchanged until the state of the counter 27 is equal to the state of the counter 26 and a signal does not appear at the output of the comparator 29. Next, the process of entering information is as described;

- restoration of channel clock pulses. When reproducing information from a magnetic recorder, malfunctions are possible due to the disappearance of channel sync pulses, which is due either to a deterioration in the quality of

magnetic tape with time or failure when recording information on a magnetic recorder. In the proposed device, there is a unit for restoring channel sync pulses, which generates a new sync pulse in case of a sync pulse disappearing in a series reproduced by a magnetic recorder. The principle of operation of block 5 is that during the time interval of the supposed channel sync pulse, a signal of the so-called temporary gate is formed and if during the time of existence of this signal the expected sync pulse

not for wils, temporary gate

then at the end of the signal ti

a new sync pulse is formed. Block 5 works as follows. Before starting, the triggers 196 and 197 are set to the initial state by a signal at input 76. The first sync pulse from the magnetic recorder enters at input 74 through element 198, the differentiating circuit 201, 202 and element 203 in counter 194, which is set to zero condition. How tol-

k counter 194 overflow - set

overflow signal

through element 193 to initial state 5

ten

25 15

20

thirty

35

40

45

55

The triggering triggers 196 and 197 and the operation of block 5 are terminated before the arrival of the sync pulse from the magnetic recorder. The number of recoverable sync pulses is equal to the maximum content of counter 194. Generator pulses 191 are passed to counter 192, the division factor of which is determined by the conversion factor specified from register 190, through element 199 is fed to counter 204, which determines the position of the time gate signal. The signal of the counter 204 of one output is the front edge of the signal of the temporary gate, and the signal of the other output is the rear. The signal of the counter 204 forms a recovered clock pulse. The same signal increases the content of the counter 194 of the number of recovered clock pulses. The pulse of the recovered clock pulse is transmitted to control unit I;

- conversion of a serial time code. The conversion of a sequential time code into a parallel code is performed at code receiver 30 as follows.

A sequential time code from the magnetic recorder through blocks 2 and 1 at input 131 enters receiver 30 on a single vibrator 233. The output signal of a single-vibrator 233 through element 237 enters the input of trigger 235, setting it to 1 times more is the time stamp and after it the next time code bit having state 1. Upon completion of the output signal of the 233 one-shot, the trigger 235 is set to the state O. The output signal of the trigger 235 is transmitted to the inputs of the parallel or sequential register recording 250 is determined by the location of the bit following the timestamp, either in the higher order of the output parallel time code transmitted through the switch 33 to the computer on output 152, or in the younger.

"

The sequence of states of the trigger 235 characterizes the state of the bits of the sequential time code.

All of these states are sequentially written to register 250 after the last bit of the sequential time code is received by the trigger 236 in this register and transmitted through element 245.

171529231

The parallel time code transmits to the computer with each frame sync,;

Register 250 is set to a state with a signal from element 245.

in with with and x in n in h t

Formula of Invention

A device for inputting information comprising a control unit, an interface unit, a recording control unit, a second signal conditioner, a code receiver, a second switch, an information input, a time code input, and inputs of the channel and frame sync pulses of the interface unit are the first input of the control unit is connected to the first output of the recording control unit; the gating input of the second switch is connected to the first output of the control unit; the output of the second controller 30

35

40

The signal bodies are informational 25; the installation inputs of the first, third, fourth and ninth flip-flops are connected respectively to the eleventh through fourteen control units; the reset input of the sixth flip-flop is connected to the installation input of the seventh flip-flop; the sync inputs of the second, third, sixth and eighth flip-flops connected to the outputs from the fifteenth to the eighteenth control block, the inverse output of the first trigger is connected to the information input of the third trigger, the direct output of which is Inen with the pulse generator input, the information outputs of the second counter are connected to the information inputs of the fourth register, the address inputs of the first memory block and the information inputs of the second decoder, the write-read inputs, the chip selectors and the information memory of the first memory block are connected respectively to the direct the output of the ninth trigger, with the outputs of the second decoder and with the direct output of the fifth trigger, the information input of which is connected to the nineteenth output of the control unit, the output of the first block pa The memory is connected to the information input of the sixth trigger, the direct output of the seventh trigger is connected to the gate input of the second decoder, the synchronous input of the third register is connected to the twentieth output of the control unit, twenty

output of the device, characterized in that, in order to simplify the device and increase its noise immunity, a negating mode mode, a clock recovery unit, the first signal conditioner, first to ninth triggers, the first and second memory blocks, the first and the second decoders, the first to the fourth counters, the pulse generator, the first switchboard, the first to the fourth registers and the TPP code comparators, the inputs from the second to the ninth control unit are information inputs of the device, the information input the first register, the logic zero input of the first trigger, the signal inputs of the logic unit of the seventh and eighth flip-flops, the reset input of the sync pulse recovery unit and the inputs from the first to the fourth recording control unit are the control inputs of the device, the second output of the control unit, the first output of the code receiver, the output the second switch, the second and third outputs of the recording control unit, and the outputs for switching on and off the tape drive mechanism of the first shaper of signals are the control circuits of the a, the output of the clock recovery unit is connected to the tenth INPUT of the control unit, the eleventh and twelve entries of the 45

50

55

0

0

18

connected to the first and second outputs of the controller, inputs from the thirteenth to the eighteenth control units are connected respectively to the direct outputs of the eighth, second triggers, first decoder, to the direct outputs of the first, sixth and fourth triggers, the ready input of the second switch is connected to the first output of the receiver code, the reset inputs of the first, second and fifth to ninth flip-flops are connected respectively to the outputs from the third to the eighth control unit, the reset input of the second flip-flop is connected to the reset input On the third trigger, the reset input and the fourth trigger are connected to you-. the overflow of the second counter, the reset input of the ninth trigger is connected to the synchronous input of the fifth trigger, the reset inputs and clocks of the second counter are connected respectively to the ninth and tenth outputs of the control unit 30

25

35

25

40

25

25

45

25

50

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55

1915

The first output of which is connected to the first control input of the second compiler, the information input, the sync input and the set and reset inputs of the receiver code are connected to the twenty third output of the control unit, the recording input of the sync pulse recovery unit connected to the twenty-third

the output of the control unit controlling Q respectively with the output of the first pe

15

20

the code receiver path is connected to the second control input of the second switch, with the third register output, with the input of the first driver: ignals, with the control input of the sync pulse recovery unit and with the first control input of the mode setpoint, the first and second information inputs of the second the switch is connected to the second and third outputs, the code receiver, the recording entry of the fourth register is connected to the fourth output of the code receiver, the third information input of the second switch is connected to the output of the fourth register, 25 Records of the second memory block are connected to the twenty-fourth output of the control unit, the reset inputs of the third and fourth counters are connected to the twenty-fifth output of the control unit, Q ramp, the second control input of the setting mode, inputs from the fifth through fourteenth control unit of the record connected to the twenty-sixth stroke of the control unit; the control input of the interface unit is connected to the first output of the mode setter; the recording input of the first register is connected to the third output of the interface unit,

input channel sync pulses block

40

.35

the histories and the output of the first switch; the information inputs of the second register are connected to the outputs of the second memory block; the record input of the second register is connected to the fourth output of the record control block; the information inputs of the second driver. The second register is connected to the outputs of the second register, the second signal generator 1 is connected to the fifth output of the recording control unit and the fourth counter clock input, the fifteenth input of the writing control unit is connected to the code comparator output, the third counter clock input is connected to the sixth output the recording control unit; the outputs of the third counter are connected to the first information inputs of the first switch and the code switch; the outputs of the fourth counter are connected to the second information inputs of the first switch and comparator codes w conductive control input of the first switch is connected to the seventh output recording control unit. The clock input of the first counter is connected to the output of the pulse generator, the inputs of the first decoder are connected to the outputs of the first counter. .

20

The clock recovery is connected to the fourth output of the interface unit. The information input, the reset inputs and the first register settings are connected to the second, third and fourth outputs of the mode setter respectively, the information and address inputs of the second memory block are connected

one

15

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40

35

the histor and the output of the first switch, the information inputs of the second register are connected to the outputs of the second memory block, the record input of the second register is connected to the fourth output of the record control block, the information gates of the second driver. Connected to the outputs of the second register, the gate input of the second signal generator 1 is connected, to the fifth output of the recording control unit and the clock input of the fourth counter, the fifteenth input of the recording control unit is connected to the output of the code comparator, the clock input of the third counter is connected to the sixth output of the control unit recording, the outputs of the third counter are connected to the first information inputs of the first switch and the code switch, the outputs of the fourth counter are connected to the second information inputs of the first and comparator switch codes, a control input of the first switch is connected to the seventh output recording control unit. The clock input of the first counter is connected to the output of the pulse generator, the inputs of the first decoder are connected to the outputs of the first counter. .

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Claims (1)

Claim An information input device comprising a control unit, an interface unit, a recording control unit, a second signal conditioning instrument, a code receiver, a second switch, an information input, a time code input, and channel and frame clock inputs of the interface unit are the device inputs of the same name, the first input the control unit is connected to the first 20 output of the recording control unit, the gate input of the second switch is connected to the first output of the control unit, the output of the second signal conditioner is information the 25th output of the device, characterized in that, in order to simplify the device and increase its noise immunity, it includes a mode sensor, a clock recovery unit, a first signal conditioner, first to ninth triggers, the first and second memory blocks, the first and the second decoders, from the first to the fourth counters, the $$ pulse generator, the first switch, from the first to the fourth registers and the code comparator, the inputs from the second to the ninth control unit are the information inputs of the device, the information third register stroke, logical zero input of the first trigger, logic signal inputs of the seventh and eighth triggers, reset input of the clock recovery block and inputs from the first to fourth recording control blocks are the control inputs of the device, the second output of the control unit, the first output of the receiver code, the output of the second gg switch, the second and third outputs of the recording control unit and the on and off outputs of the tape drive mechanism of the first signal conditioner are control outputs 55 devices, the output of the clock recovery unit is connected to the tenth input of the control unit, the eleventh and twelfth inputs of which are connected to the first and second outputs of the interface unit, the inputs from the thirteenth to eighteenth of the control unit are connected respectively to the direct outputs of the eighth, second triggers, the first decoder, with direct outputs of the first, sixth and fourth triggers, the readiness input of the second switch is connected to the first output of the code receiver, the reset inputs of the first, second and fifth through ninth tr ggerov connected respectively to the outputs of the third to eighth block upravleniyavhod reset the second flip-flop is connected to the reset input of the third flip-flop, a reset input and a fourth latch connected to Vyg. during the overflow of the second counter, the reset input of the ninth trigger is connected to the sync input of the fifth trigger, the reset inputs and the clock of the second counter are connected respectively to the ninth and tenth outputs of the control unit, the installation inputs of the first, third, fourth and ninth triggers are connected respectively to the outputs from the eleventh to fourteenth blocks control, the reset input of the sixth trigger is connected to the installation input of the seventh trigger, the sync inputs of the second, third, sixth and eighth triggers are connected respectively with outputs from the fifteenth to eighteenth control unit, the inverse output of the first trigger is connected to the information input of the third trigger, the direct output of which is connected to the input of the pulse generator, the information outputs of the second counter are connected to the information inputs of the fourth register, with the address inputs of the first memory block and the information inputs of the second decoder, the entries read-write, select the chip and the information of the first memory block are connected respectively to the direct output of the ninth trigger, with by the moves of the second decoder and with the direct output of the fifth trigger, the information input of which is connected to the nineteenth output of the control unit, the output of the first memory unit is connected to the information input of the sixth trigger, the direct output of the seventh trigger is connected to the gate input of the second decoder, the third input is connected to the twentieth the output of the control unit, the twenty-first output of which is connected to the first control input of the second switch, an information input, a sync input, and inputs for setting and resetting the receiver As the code is connected to the twenty-second output of the control unit, the recording input of the clock recovery unit is connected to the twenty-third output of the control unit, the control input of the code receiver is connected to the second control input of the second switch, with the output of the third register, with the input of the first signal conditioner, with a control input unit zosstanovleniya clock and the first control input of the set point mode, the first and second data inputs of the second switch connected to the second and third outputs' _(FOSTER As for the code, the recording input of the fourth register is connected to the fourth output of the code receiver, the third information input of the second switch is connected to the output of the fourth register 25, the recording input of the second memory block is connected to the twenty-fourth output of the control unit, the reset inputs of the third and fourth counters are connected to the twenty-fifth output of the up-, θ equalization block, the second control input of the mode setter, the inputs from the fifth to fourteenth of the write control block are connected to the twenty-sixth output of the control block, control input b the interface is connected to the first output of the mode master, the first register entry is connected to the third output of the interface unit, the input of the channel clock of the _ recovery clock module is connected to the fourth output of the interface, the information input, reset and first register settings are connected respectively to the second, third and fourth outputs of the mode switch, the information and address inputs of the second memory block are connected respectively to the output of the first register and to the output of the first switch, and the information inputs of the second register are connected to the outputs of the second memory block, the recording input of the second register is connected to the fourth output of the recording control unit, the information-digital inputs of the second driver are connected to the outputs of the second register, the gate input of the second driver>. the signals are connected to the fifth output of the recording control unit and to the clock input of the fourth counter, the fifteenth input of the recording control unit is connected to the output of the code comparator, the clock input of the third counter is connected to the sixth output of the recording control unit, the outputs of the third counter are connected to the first information inputs of the first switch and code switch, the outputs of the fourth counter are connected to the second information inputs of the first switch and code comparator, the control input of the first switch is connected to dmym output of the first counter recording control unit, a clock input connected to the output of the pulse generator, the inputs of the first decoder coupled to outputs of the first counter. Figa ΐ 529231 Fig.13 FIG. 2 52.53.54.55 4 ⁺ * l; "p U χ ..... ". . " -C / w ^g 1 o-h FIG. 5 Compiled by S. Kulish ' _h Editor A. Ogar, Tehred L. Serdyukova Corrector M. Sharoshi ’ Order Circulation 668 Subscription VNIIIPI of the State Committee for Inventions and Discoveries at the State Committee for Science and Technology of the USSR 113035, Moscow, Zh-35, Raushskaya nab., 4/5 Production and Publishing Plant Patent, Uzhhorod, st. Gagarina, 101