SU1476618A1 - Device for determining pauses in speech - Google Patents

Abstract

The invention relates to telecommunications. The purpose of the invention is to detect speech pauses both in a system with pulse code modulation and in a system with delta modulation. The device has a main channel 1 containing registers 2 and 3, a reversible counter 4, elements OR 5 and 6, RS flip-flop 7, switches 8.9 and 10, D-flip-flops 11 and 12, counters 13.14 and 15, keys 16 , 17 and 18, the decoder 19 and the inverter 20, as well as an additional channel 21 containing the key 22 and the combination unit 23 channels. When speech information arrives at the device input, this device provides a reliable selection of the beginning of words and separate semantic fragments of speech, starting with explosive sounds, especially critical to the accuracy of the analysis, and does not respond to separate short noise pulses. 1 il.

Description

The invention relates to telecommunications and can be used to detect pauses in speech transmitted using both pulse-code (PCM) and delta modulation (DM), in particular, in speech compression systems with additional information.

The purpose of the invention is the detection of speech pauses both in a system with pulse-code modulation and in a system with delta modulation.

The drawing shows a structural electrical diagram of a device 15 for detecting pauses in speech.

The device contains a main channel 1, containing the first and second registers 2 and 3, a reverse counter 4, the first and second elements OR 5 and 6, 20

RS-flip-flop 7, first-third switches 8-10, first and second D-flip-flops 1 1, 12, first-third counters 13-15, first-third keys 16-18, decoder 19, inverter 20, and also 25, an auxiliary channel 21 comprising a fourth key 22 and a channel combining unit 23.

A device for detecting pauses βθ of speech works as follows.

Information from an external speech-converting device (PCM encoder) comes in the form of samples of a PCM signal in a serial code to the first input of the device. Each PCM-from-; the account is represented by code switching from K digits. When k = 8, the most significant bit of the code combination carries information about the sign of the analog speech signal, and the remaining bits characterize its level. Information is recorded in shift register 2 with a clock frequency that is supplied to the clock input of register 2 d§ (second input of the device) from the PCM encoder. Since in the silent mode, due to the noise background and other reasons, units may appear in the four least significant bits of the code combinations, the information for deciding on the subscriber's transition to the active, active state is the appearance of units in the three highest bits of the count. Additional outputs of register 2, $$ corresponding to the three most significant bits of the speech signal level are connected to the inputs of the OR element 5, The signal from the output of the OR element 5 is fed to the corresponding input of the switch 8. The information signal from the output of the delta encoder is fed to the third input of the device. In register 3, a digital delta-modulated signal is recorded at the moments of arrival of pulses of frequency fq at the fourth input. In parallel, the delta-modulated signal is fed to the control input of the reverse counter 4, translating it into the summation or subtraction mode. In the case of the presence of signal 1 at the third input of the device, the reverse counter 4 switches to the mode of summing pulses arriving at the fourth input of the device. The signal 0 ”at the third input of the device puts the reversing counter 4 in the subtraction mode. Thus, the current state of the reverse counter 4 reflects the level of the speech signal. In this case, the code of the reverse counter 4 can be considered as a code combination of the PCM signal. Similarly to the case of the PCM signal, the potentials from the three most significant bits of the reversible counter 4 · are supplied to the OR element 6. The signal from the output of the OR element 6 is fed to the corresponding input of the switch 8. When working with the PCM encoder, the RS-flip-flop 7 receives frequency pulses arriving at the second input is set to a single state. In the case of using a delta encoder, the RS-flip-flop 7 with pulses of frequency f ₂ supplied to the fourth input is set to 0 ”.) Thus, the signal from the output I of the RS-flip-flop 7 corresponds to the use of a specific type of encoder that works with the device. The RS-trigger 7 controls the operation of the first switch 8, with a single signal from its output, the output of the OR element 5 is connected to the corresponding input of the key 18, and when the signal from the output of the RS-trigger 7 is zero, the output of the OR element 6 is connected. The switches 9 and are controlled similarly. 10. So, if RS- · .. trigger 7 is in a single state, then the output of register 2 through the switch 10 is connected to the corresponding input of the key 17, and the fifth input of the device through the switch 9 ~ to the corresponding input of the key 18.

Otherwise, the output of the register 3 is connected to the output of the key 17, and the output of the D-flip-flop 12 is connected to the input of the second key 18, which generates a signal with a frequency of 8 kHz from the + signal input to the fourth input from the delta encoder. Thus, at the output of switch 9, both in the case of operation of the device with an PCM encoder and a delta encoder, a signal with a frequency equal to 8 kHz will be present. The pulses of this frequency are calculated by a counter with a conversion factor N = 320, which determines the observation interval t _H = N / f3 = 40 ms (the time during which the information in registers 2 and 3 will be completely replaced for cases when the device operates with delta or PCM- encoder, respectively). Transfer pulses at the output of counter 13 appear with a period of 40 ms and set to 0 ”counter 15. If there is at least one unit in the three high-order bits 4 and the outputs of register 2 or reversible counter 4, the corresponding elements of OR 5 or 6 form signal 1, which through the switch 8 allows the passage of pulses of frequency 8 kHz from the output of the switch 9 to the counting input of the counter 15. The conversion factor of the counter 15 is selected from the following considerations. Firstly, the device for detecting pauses in speech should not respond to stand-alone short (up to 10 ms) noise impulses, and secondly, it should reliably highlight the beginning of words and individual semantic fragments of speech starting with explosive sounds, especially critical to the accuracy of analysis ”

If we assume that a separate noise pulse will have all the samples of a large level, then in 10 ms a maximum of 80 sampling frequency pulses will arrive through key 17. Therefore, the conversion factor of the counter 15 is chosen equal to 80. Such a coefficient will provide, on the one hand, cutting out short freestanding noise pulses, and on the other hand, will reliably classify the beginning of words and semantic fragments of speech even in the case of the most mouth phonemes. In the event that the subscriber is silent, then the counter 15 will not have time to count the required number of pulses and will be periodically set to 0 by the transfer pulse from the output of the counter 13 at the end of each observation interval.

When the subscriber enters the active state, the counter 15 for the duration of the observation interval (40 ms) will have time to count the required number of pulses and generate a transfer pulse at its output, which will set the D-trigger 11 at the input S to the single state, and the counter 14 to the zero state. The signal from the direct output of the D-flip-flop 11 allows the passage of the transfer pulses of the counter 13 through the key 16 to the input of the counter 14. In this case, the transfer pulse of the counter periodically sets the counter 14 to zero. The counter 14 is designed to delay the release of the speech channel for a time of the order of 160-200 ms after the subscriber switches from conversation to silence. The transfer pulses of the counter 13 follow with a period of 40 ms, therefore, to ensure a delay in releasing the main channel of 160-200 ms, the conversion factor of the counter 14 is set to I = 5-6.

When the subscriber switches from conversation to silence, the D-trigger 1J is in a single state, which ensures the passage of pulses from the output of the key 16 to the input of the counter 14, which has a given number of pulses. At the same time, a signal appears at the output of the decoder 19, setting the D-trigger 11 at the input R to the zero state. In this case, the key is closed, which will ensure that the state of the counter 14 is preserved, and therefore the corresponding signal is saved at the output of the decoder 19. Thus, after 160-200 ms after the subscriber is silent, the key is closed and the key 22 is opened, which will provide a connection to the input 'block 23 of the additional channel 21.

Upon the transition of the subscriber to the active state, the D-trigger 11 will again be set to a single state, and the counter to zero. When this signal from the output of the decoder 19 is changed to

I opposite, which leads to the opening of the key 17 and the lock key 22.

Claims (1)

Claim A device for detecting pauses in speech, containing the main and additional 1476618 channels, the main channel containing the first register, the information and clock inputs of which are the first and second inputs of the device, respectively, the first outputs of the register are connected to the inputs of the first OR element, the first counter is connected in series, the first a key, a second counter and a decoder, the output of which is connected to the inverter output, the first input of the second key and the first input of the first trigger, the second input of which is connected to the second input the second counter and the output of the third counter, the first input of which is connected to the output of the third key, the first input of which through the first counter is connected to the second input of the third counter, the output of the first D-trigger is connected to the second input of the first key, and the additional channel contains the fourth key in series and a channel combining unit, the output of which is the output of the device, the second input of the channel combining unit connected to the output of the second key, and the first input of the fourth key connected to the output of the inverter, characterized in that, in order to detect speech pauses both in a system with pulse-code modulation and in a system with delta modulation, a second register, a reverse counter, a second OR element, an RS-trigger, a second D-trigger, the first, the second and third switches, ₅ wherein the information input of the second register is combined with the control input of the reversible counter and is the third input of the device, the clock input of the second register is combined with its corresponding inputs of the reverse counter of the RS-trigger and the second D-trigger, and is four the first input of the device, the outputs of the reverse counter through the second OR element are connected to the first input of the first switch, the second input of which is connected to the output of the first OR element, the clock input of the first register is combined with the second input of the RS-trigger, the second output of which is connected to the control inputs of the first, of the second and third switches, respectively, the output of the second D-trigger through the second switch is connected to the first input 25 of the third key, the second input of which is connected to the output of the first switch, the first and second inputs of tego switch connected to the second output of the first register and the second register vy30 stroke respectively a third switch output is connected to the second input of the second switch and the second input of the second switch is the fifth input device.