SU1325717A1 - Detector of pauses in speech in system with delta-modulation - Google Patents

Abstract

This invention relates to a multichannel communication and provides improved accuracy in detecting speech pauses. The speech pause detector contains in the main channel 1. shift register 2, elements 3, 4, 5, counters (C) 6, 7, delay element 8, triggers 9, 10, channel hold time counter 11, decoder 12, inverter 13, block 14 combines the signals, and in additional channel 17, an And 18 element. At input 16, a clock frequency is supplied, and at input 15, information is given in sequence. code from the delta decoder. C 6 sets the duration of the observation interval t, His transfer impulse sets C 7 to O. When the subscriber is silent, input 15 receives a sequence of silence code in the form of a meander, which has a certain number N of transitions from 1 to O at interval t 1. The transfer impulse C 7 sets D trigger 10 to state O, acc. silent subscriber. In this case, the signal from the D-flip-flop 10 prohibits the passage of the transfer pulse C 6 through the element I 4 during two periods of the clock frequency. When the subscriber transitions to C 7 activity for period t, he doesn’t have time to count N and N, and C 6 sets the D-flip-flop 9 to 1, and counter 11 to O, Counter 11 delays SO release of channel 1 after the subscriber transitions from activity to silence. the subscriber’s transition from conversation to silence at the D-flip-flop 9 signal through the And 5 element at the counter 11 impulses p: Transfer C 6. When the counter 11 is counting a specified number, the signal of the decoder 12 will set the D-flip-flop 9 in O. through the element And 18 block 14 passes the information from the additional channel 17. 1 Il. g (L 00 I4D SP Nl

Description

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The invention relates to multichannel communication, in particular to signal-compaction systems with delta modulation.

The aim of the invention is to improve the accuracy of speech pauses. Pa the drawing shows a flow chart for detecting speech pauses in a system with delta modulation.

The detector mainly contains the canap 1 shift register 2, the first 3, the second 4 and the third 5 elements AND, the first c4et4HK 6, the second counter 7, the delay element 8, the first 9 and the second 10 trigger, the channel hold time counter 11, the decoder 12 Inverter 13, unit 14 of signal coupling, informational input 15 of the main channel, input 16 of the clock frequency f, and the fourth element AND 18 is included in the additional channel 17 D-triggers are used as triggers.

 The speech pause detector in a delta-modulation system operates in the following manner.

The information from the delta coder is fed in a sequential code with a speed of V bps to the input 15 of the master channel 1. Information is written to the shift register 2 at a frequency f equal to V, which is generated at the encoder and fed to the input 16 devices. In order to reliably highlight the shortest phonemes corresponding to explosive sounds 1C, g, b, etc., the duration of which lies within 20-25 ms, the observation interval t is chosen to be 40 ms. In this regard, the shift register 2 at VP of 16 kbit / s must have a capacity of K Vf, bit, i.e. contain K binary bits.

When the subscriber is silent, the delta coder enters input 15 of the sequence of the silence code 101010 ... Due to the background of the room, this sequence may be disturbed, i.e. instead of the meander corresponding to the silence code, bursts O and 1 are formed at the output of the delta coder. The duration mjTMOBbix t of pulses, causing the appearance of such bursts, as a rule, does not exceed 10 ms. In this case, the speech pauses detector in the system with delta modulation j, firstly, should not respond to separate short (up to 10 ms) noise impulses, secondly, should reliably distinguish the beginning of words and individual cm1 fragments speech beginning with explosive sounds, especially critical to the accuracy of the analysis.

When the code is silent the number of transitions

from r

 O in the delta coder digital sequence over the duration of the observation interval t is a. If we assume that a short separately standing noise pulse is represented by a digital sequence consisting of only 1 (or only O), then if the subscriber is silent during the observation interval t, the number of transitions from 1 to O in the digital sequence of cases, the coder decreases on t, yf, // 2 compared to the silence code. Considering the latter, for cutting out separately standing noise impulses, the coefficient of recalculation N of counter 7 is determined from the equality () / 2

Note that the duration of the observation interval tj is defined by counter 6, which, with its I1 transfer pulses, periodically sets counter 0 to O. In this case, the conversion factor of the counter 6 is numerically equal to the capacity of the register 2 shift.

Thus, when the subscriber is silent, the counter 7 for the duration of t has time to count the specified number of transitions N from 1 to O. At this, the counter 7 generates a transfer pulse at its output, which sets the D-flip-flop 10 via the R input to the zero state corresponding to silence subscriber. The signal from the direct output of the D-flip-flop prohibits the transfer of the transfer pulse generated by the counter 6 through the element 4. After the completion of the transfer pulse of the counter 6, the D-trigger 10 at the C-input returns to the logical 1 state passing through the delay element 8, which provides a delay of two periods of the clock frequency f (signal 1 at the D input of the trigger 10 is not shown).

When the subscriber transitions from silence to activity, packets O and 1 of sufficient volume are formed at the output of the delta coder. As a result, the number of transitions from 1 to O is sharply reduced compared to the silence code, counter 7 during period t. fails to count to N, and D-trigger 10

3

According to

remains in the unit state, the end of the observation period t output of the counter 6 generates a transfer pulse, which passes through the element 4 and converts the trigger point 9 to the unit state via the S input D and the channel hold time counter 11 is zero condition. Note that when the subscriber is active, the transfer pulse from counter 6 through element 4 is periodically set to: - 11 in the zero state. The channel hold time counter 11 performs the function of an inertial element that is designed to delay the release of the main channel for about 160-100 ms after the subscriber transitions from the active state to the silent state. nig. A delay in releasing the main channel is necessary to absorb short interruptions in continuous speech that are not audible.

The transfer pulses from counter 6 follow with a period t of 40 ms, therefore, the dp of providing a release delay of the main channel of 160-200 ms, the conversion factor of counter 11 is assumed to be large 4-5.

When the subscriber goes from talking to silence, the D-flip-flop 9 saves a single state, which ensures the transfer of transfer pulses from the output of counter 6 through element 5 to the counting input of counter 11. As the subscriber is silent, then by the corresponding input of the periodic installation in the counter O 11, the channel holding time is not produced, and this counter has a predetermined number of transfer pulses arriving through the element 5. At the output of the decoder 12, a signal appears that sets the D-flip-flop 9 to the C input to the zero state ( The signal O on the D input of the trigger 10 is not shown).

 The signal from the output of the D-flip-flop 9 prohibits the passage of the transfer pulses of the counter 6 through the element 5, which ensures that the state of the counter 11 is preserved, and consequently, the corresponding signal is saved at the output of the decoder 12, which controls the operation of the elements 3 and 18 through the inverter 13. Thus, when the subscriber is silent, the information is passed

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from the additional channel 17 through the element I 18 and the block 14 combining signals to the output of the device.

When the subscriber transitions to the active state, the D-flip-flop 9 through the S-input is again set to one, and the counter 11 to the zero state. At the same time, the signal from the output of the decoder Q 12 is changed to opposite.

which ensures the passage of information from the output of the shift register 2 through the emitter And 3 and the block 14 of combining signals to the output of the device.

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five

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Formula of invention

A speech pause detector in a delta-modulated system, containing, in the main channel 1, the first And element, the delay unit, the second And element, to the first input of which the input of the third And element is connected, in order to improve the accuracy of detecting pauses of speech , an additional channel containing the I element is entered into it, and the shift channel, the first counter and the trigger, the signal combining block, the first input of which through the first element I connects the output of the shift register, to the information input of which through entered in series the second counter, the second trigger is connected to the second input of the second element I, the output of which through the first trigger is connected to the second input of the third element I, the output of which through the serially connected counter of the channel retention time, to the second input of which the output of the second element I and the decoder is connected respectively to the first input of the inverter, the first input of the first trigger and the second input of the first element I, and to the clock input of the shift register through o connected the first counter, the output of which is connected to the input of the second counter in O and the first input of the second element AND, the delay element is connected to the second input of the second trigger, while the output of the inverter and the second input of the signal combining unit are connected respectively to the first input and output of the AND element additional channel.

Claims (4)

Claim Detector of speech pauses in a system with delta modulation, containing, in the 0 main channel, the first element And, a delay unit, the second element And, the first input of which is connected to the input of the third element And, characterized in that, in order to increase the accuracy of detection of speech pauses , an “additional channel” is introduced into it, containing the AND element, and in the main channel, the shift register, the first counter and trigger, the combining unit are entered About signals, to the first input of which through the first element AND the output of the shift register is connected, to the information input of which through the second series 5 counter, the second trigger is connected to the second input of the second element And, the output of which through the first trigger is connected to the second input of the third element And, the output of which is not entered through the input, and this counter has a given number of transfer pulses coming through the element And 5. At the same time, decoder output 1- 2, a signal appears that sets the D-flip-flop 9 at the C-input to the zero state (supply of signal 0 to the D-input of flip-flop 10 is not shown). The signal from the output of the D-trigger 9 prohibits the passage of transfer pulses of the counter 6 through the element And 5, which ensures the conservation of the counter 11, and therefore, the preservation of the corresponding signal at the output of the decoder 12, which controls the operation of the elements And 3 directly, and And 18 through the inverter 13. Thus, when the subscriber is silent, information is passed through the series-connected channel hold-down time counter, to the second input of which the output of the second element And is connected, and the decoder is connected respectively to the first ₄ May inverter input, the first input of the first flip-flop and a second input of the first AND gate and to the clock input of the shift register through the serially connected first counter whose output is connected to the set input of G second counter and the first input of the second AND gate and a delay element connected to the second the input of the second trigger, while the inverter output and the second input of the signal combining unit are connected respectively to the first input and output of the AND element of the additional channel.