SU1411989A2 - Detector of speech pauses in delta-modulation system - Google Patents

Abstract

The invention relates to communication technology. The aim of the invention is to improve the accuracy of the detection of speech pauses in conditions of a change in the level of the ambient noise background. The device contains the main channel 1, the shift register 2, the elements And 3,4,5, D-flip-flops 9,10, the channel holding time counter 11, the decoder 12, the signal combining unit 14, the information input 15 of the main channel, 16 clock input frequency f, additional channel 17. In order to increase the accuracy of speech pauses detection, an inverter 13, subtraction counter 19, averaging interval counter 20, storage register 21, noise level decoder 22, control signal generating unit 23, additional delay element 24, OR 25, element AND 26. 1 il. with s

Description

R

(L

four

QD 00 (

 1H

The invention relates to communication technology, in particular to signal multiplexing systems with delta modulation, and is an improvement to the invention in the author. No. 1325717,

The aim of the invention is to improve the accuracy of detecting pauses of speech under the conditions of a change in the level of the ambient noise background.

The drawing shows a structural electrical circuit for detecting speech pauses in a system with delta modulation.

Speech pause detector in a system with delta modulation Contains the main channel 1, the shift register 2, the first 3, the second 4 and the third 5 And elements, the first counter 6, the second counter 7, the delay element 8., the first 9 and the second 10 triggers, a channel holding time counter 11, a decoder 12, an inverter 13, a signal combining unit 14, a main channel information input 15, a clock frequency input f - 16, an additional channel 17, a fourth And 18 element, a subtracting counter 19, an averaging interval counter 20, a register 21 storages, depot rator 22 noise level, block 23 control signal, additional delay element 24, element OR 25, fifth element AND 26, B. As a trigger, a D trigger is used. The speech pause detector in a delta-modulation system operates as follows.

The information from the delta coder is received, in a serial code with bit rate / s at the input 15 of the main channel 1, the information is written to the shift register 2 at a frequency f equal to V, which is formed in the encoder and fed to the input 16 . To reliably distinguish the shortest phonemes corresponding to explosive sounds k, n, b and t, d „, the duration of which lies in the range of 20-25 ms, the observation interval t lies in the range of 30 ms

t. 300 ms Register 2 shift

wives have a capacity of K., (i.e. contain K binary bits)

When the subscriber is silent from the delta coder, it enters the input 15 of the sequence of the silence code 1010101 "o. Due to the background of the room, this sequence may be disrupted, i.e., instead of the meander corresponding to

0

0

in silence, a bundle of zeros and ones are formed at the output of the delta coder. The duration of the noise pulses causing such bursts lies in the range of 5–15 ms. At the same time, the speech pause detector in the system with delta modulation should not respond to noise pulses. It should also reliably distinguish the beginning of words and separate semantic fragments of speech, beginning with explosive sounds, especially critical to the accuracy of the analysis.

When the code is silent, the number of transitions from 1 to O in the digital sequence of the delta coder on the duration of the observation interval t is t If we assume that noise pulses with a total duration t are represented by a digital sequence consisting only of ones (or only zeros), when the subscriber is silent for the duration of the observation interval tc, the number of transitions from 1 to O in the digital sequence of the delta coder is reduced by tm compared to the silence code. Considering the latter, to cut noise pulses into pa In terms of speech, the conversion factor N of the counter 7 is determined from the equality N f () / 2.

The duration of the observation interval tj is defined by a counter 6, which periodically sets its counter impulse 7 to its transfer pulse. The recalculation coefficient of counter 6 is numerically equal to the capacitance of shift register 2 K t., F ,.

tЦТ

I

Thus, when the subscriber is silent, the counter 7 for the duration t will have time to count the specified number of transitions AND from 1 to Oo. At the same time, the counter 7 will generate a transfer pulse at its output, which sets the D-flip-flop 10 at the R input to the zero state corresponding to the subscriber's silence. from the direct output of Trigger 10 prohibits the passage of the transfer pulse generated by counter 6 through element 4 ;, After the end of the transfer pulse of counter 6, D-flip-flop 10 at input C returns to the state of logical unit by passing through 8 lement delay which provides a delay of two cycles Tacto u

frequency f (signal 1 on the D-input of the trigger 10 is not shown).

When the subscriber transitions from silence to activity, packets of zeros and units of sufficient volume are formed at the output of the delta coder. As a result, the number of transitions from 1 to O is sharply reduced compared to the silence code, counter 7 for the period tj does not have time to count to N and the trigger

10 appears in the unit state. At the end of the observation period 1c, a transfer pulse is generated at the output of counter 6, which passes through AND 4 and translates input S to D-flip-flop 9 into one state, and Hold channel counter 11 is set to zero state When the subscriber is active, a transfer pulse from the output of counter 6 through element 4 automatically sets the counter

1I is in zero state. The channel hold time counter 1I plays the role of an inertial element, which is designed to delay the release of the main channel for about 160,200 ms, after the subscriber transitions from active state to silence. The release delay of the main channel is necessary to absorb short unequals in the fused speeches that are not audible, but are inherent in her very nature with

The transfer pulses from the output of counter 6 follow with a period t, therefore, to ensure a release delay of the main channel t (in 160-200 ms the conversion factor M of counter 11 is from the condition M L t, where L J is rounding to the nearest upper integer "

When the subscriber goes from conversation to silence, trigger 9 retains a single state, which ensures the transfer of transfer pulses from the output of counter 6 through the element 5 to the counting input of counter 11. As the subscriber is silent, then the corresponding input of the periodic installation of the channel hold time 11 to zero is not produced, and the counter 11 feeds the specified number of transfer pulses arriving through the AND 5 element at the output of the decoder

12po is a signal that sets the D-flip-flop 9 on input C to the zero state (giving signal O to D1989

trigger input 9 is not shown) The signal from the trigger output 9 prohibits the passage of transfer pulses of the counter 6 through the element 5, which ensures that the state of the counter 11 is preserved and, consequently, the corresponding signal is saved at the output of the decoder 12, which controls

0 by the operation of the elements And 3 directly, and the element And 18 through the inverter 13. Thus, when the subscriber is silent, the information from the additional channel is passed

5 17 through the element And 18 and the block 14 combining signals to the output device

When the subscriber enters the active state, D-flip-flop 9 is again set to one state, and

0 counter 11 - to zero. In this case, the signal from the output of the decoder 12 is reversed, which ensures the passage of information from the output of the shift register 2 through the element

5 and 3 and block 14 of the combination of signals to the input device

Elements 19-26 included in the device circuit ensure its operation in the adaptive mode: in speech pauses

0, an estimate of the value of t is made for the duration of the averaging interval t, then, in accordance with the obtained estimate tyj, a new value of the conversion factor N is established

counter os 7,

The change of the conversion factor of the counter 7 in the device is carried out as follows.

When the subscriber is active, the signal from

0 output of the decoder 12 enters through the OR element 25 to the input of the subtracting counter 19 and directly to the input of the counter 20 of the averaging interval, keeping them in the single and nu45 left state, respectively. When the subscriber transitions from activity to silence, the decoder code changes. on the opposite, which provides the ability to work

eg counters 19 and 20 in subtractive and summing modes, respectively. Subtractive counter 19 counts the number of transitions from 1 to O over the duration of the averaging interval to digital

from the delta modulator sequence to the input of the device 15

The duration of the averaging interval to, is defined by the counter 20, to the counting input of which the transfer pulses are generated, generated by the period t of the counter 6. Then ti, where K "is the conversion factor of the counter 20 of the averaging interval. The value of K "is set so as to ensure the choice of t in the range from 300 ms to 2 s. The latter is explained by the fact that the average duration of speech pauses during a dialogue exchange is approximately 1.67 seconds.

The recalculation factor Kg of the detracting counter 19 is numerically equal to Kg Vyty / 2o. At the time of the completion of the averaging interval, the transfer pulse from the output of the counter 20 enters through the open element AND 26 to the synchronous input of the storage register 21 by overwriting information from the lower bits of the deducting counter 19 to the storage register 21.

The capacitance Kr of the storage register 21 provides an entry in the binary code of the number V -tj -Ky / 2, i.e.

Kp loggV t Ky - ij.

where t

sh.m ke

the maximum duration of a separate standing noise pulse, which is cut by a pause detector of the same transfer pulse, passing through an additional delay element 24 and an OR 25 element, which counts the counter. 19 returns to the one state

The state of the storage register 21 is identified by a noise level decoder 22. Signals from the outputs of the decoder 22 are received at block 23, which aggregates the number of states of the decoder 22 and generates control signals to establish a corresponding conversion factor in the counter 7. The numbers of states in block 23 can be implemented on the basis of multi-input OR elements, which in a group of outputs of the decoder 22 of the noise level are combined. The number of outputs of block 23 (the number of integrated states of the decoder is 22) is equal to the number of possible

the values of the conversion factor in the counter 7 „

If the pause duration is less than the averaging interval tij, then the conversion factor in counter 7 does not change, since when the subscriber transitions to the active state, the signal from the decoder 12 output

brings the counters 19 and 20 to the initial state. The passage of the transfer pulse, which can then be formed at the output of the averaging interval counter 20, is blocked

5 prohibiting signal from the output of the inverter 13, arriving at the second input of the AND 26a element. This ensures the preservation of the contents of the register 21, and consequently, the recalculation coefficient in the counter 7,

Claims (1)

Invention Formula The speech pause detector in the system with delta modulation according to the author. No. 1325717, different 5 by the fact that, in order to increase the detection accuracy of speech pauses under the conditions of changing the ambient noise background level, a subtractive counter has been introduced, the input of which is connected to the information input of the shift register, the outputs of the subtracting counter through the serially connected stored register, the noise level decoder and the control signal generating unit is connected to the installation inputs of the first counter, the first input of the input element is connected to the output of the decoder OR - and the first input of the entered interval counter 0 averaging, the second input of which is connected to the output of the second counter, the output of the counter of the averaging interval is connected to the input of the introduced additional delay element and The input input of the input element And, the second input of which is connected to the output of the input inverter, the output of the additional delay element is connected to the second input of the OR element, the output of which is connected to the BTOpbW input of the subtracting counter, the output of the fifth element AND is connected to the control of the storage register. VSH-SPI Order 3675/57 Random polygons pr-tie, Uzhgorod, st. Project, 4 Circulation 660 Subscription