SU1233290A1 - Device for detecting pauses in speech - Google Patents

Abstract

The invention relates to telecommunications, can be used in tech. remote communication and improves the accuracy of speech detection. Before starting work, the counters 8 and 9 are set to zero, the logical zero signal is set at the outputs of the 10 and 11 triggers. The path of the main channel is made through the closed key 3 and the signal combining unit 5. The 2nd outputs of the comparing unit 2 are supplied with a binary code signal corresponding to the minimum permissible signal level in the main channel, i.e. A threshold is defined that defines the transition from speech to pause, and vice versa. When the amplitude of the speech signal decreases below the threshold value, from the 1st output of the block 32 to the 2nd input of the PL-12 the impulse arrives-. The trigger 1 1 goes into one state by closing the key 3 and opening the key 4. The overflow threshold of the counter 9 is determined by the length of pauses in the channel. From the output of the counter 9 to the input of the installation of the unit of the 2nd trigger 11, the impulse will arrive after a period of time corresponding to the pause after the triggering of the elec- tion 12. Thus, the accuracy of pause detection is performed. 1 il. C & yu with OO GO with

Description

I1

The invention relates to telecommunications and can be used in telecommunications.

 The purpose of the invention is to improve the accuracy of the detection of pauses of the furnace,

The image shows a structural electrical circuit of the proposed south-south structure.

The device for detecting speech pauses contains a delay line 1, a first comparison unit 2, first and second keys 3 and 4, a signal combining unit 5, an analog-digital converter 6, a second comparison unit 7, first and second counters 8 and 9, The second and second triggers 10 and 11, element 12, the generator 13 clock pulses.

The device works in the following manner.

Before starting, the elements of the device are in the following state. Counters 8 and 9 are reset to zero, and a logical pool signal is set at the outputs of triggers 10 and 11. The path of the main canap is made through the closed key 3 (the second input of the key 3 is fed to the control unit 2 with the trigger 11 signal of the logical unit) and the signal combining unit 5. In addition, a binary code signal corresponding to the threshold, minimum acceptable signal level in the main channel t is fed to the second inputs of the comparator unit 2, i.e. a threshold is defined that determines the transition in the main channel from speech to pause and, conversely, from pause to speech

The speech signal of the main channel is sampled and quantized in the analog-digital converter 6 with a clock frequency twice as high as the maximum frequency of the signal of the main channel (for a telephone channel the clock frequency is f; 2 x X Hz. X 8000 Hz). Such a frequency of discrimination leads to the fact that the amplitude of the samples becomes a smoothly varying vapichina and, consequently, it is possible to determine the change (increase or decrease) of the signal level in the channel, i.e. ultimately determine the channel transition from speech to pause.

At the moment when the analog-digital converter 6 arrives at the clock input of the leading edge of the clock pulse, the analog signals are converted into a digital binary code of the number corresponding to

Q

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5 g

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five

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in (Я1ре, dividing the time point to the a value of the spill of the main channel signal. The coded amplitude value of the sprg1al goes to the first inputs of comparator 2, comparator 7 and the inputs of delay line 1. Line 1 delay 1 - delays the encoded signal by 1 clock, i.e. up to the left at the first inputs of blocks 2 and 7 comparing the subsequent measured numerical value of the signal amplitude.

At the moment of arrival of the back edge of clocks, of pulses at the clock inputs of blocks 2 and 7 of the comparison, the coded values of the signals of the main channel, which are attenuated by the first 7 times and the second inputs of blocks 2 and 7 of comparison, occur. At the second inputs of the comparison unit 2, the threshold numeric value is encoded to the amplitude value of the main anapv signal. i.e., in block 2, the 1P5I compares the value of the current amplitude of the speech signal with its threshold value. With a smaller ziacheg; rp-1 amplitude of the speech signal noporoBoi o from the first output of block 2 of the sravpepi to the input of the element H 12 and the counting input of the second counter 9 receives a pulse, the larger pulse from the second code-block 2 compare the counter zero inputs 9 and EiToporo trigger 11,

Alalogically, in block 7, the code of the number corresponding to the current signal amplitude is compared with the code of the number corresponding to -) Tsego to the amplitude of the previous count, originating from the output.,., Cue 1 of the delay. If the amplitude of the current is; its signal value is less than the amplitude of the previous value, then from the first output of block 7, comparison iii-inyjibc is fed to the counting input of the first counter 8, otherwise the pulse from E: the second output of the blogg 7 compares to the first counter 8 v of the first trigger 10.

Before the appearance of a pause in the channel, the time interval of which is sufficient to connect the additional channel to the signal combining unit 5 (the overflow threshold of the first counter 8 is chosen so as not to react to short-term (fading in the main channel), the amplitude of speech samples is smoothly the output of the overflow counter of counter 8 is reduced after a predetermined time interval to the input of the unit of the unit of the first trigger 10. The trigger 10 is set to one state, opening a logic And at the first input. At the first decrease in the amplitude of the speech signal below the threshold value, the pulse from the first output of the comparison unit 2 to the second input of the element 12 comes in. Element I.12 triggers. The second trigger 1 1 goes to the single state, closing at In this case, the key 3 and opening the key 4. The overflow threshold of the second counter 9 is determined by the duration of short-term channel faults (pauses), therefore from the output (overflow) of the counter 9 to. the input of the unit installation of the second trigger 11 pulse arrives after a period of time corresponding to 1 D1 of the duration of the selected short fading (pauses), i.e. after the element And 12 already operates. Thus, the accuracy of pause detection is performed.

The transition from pause to speech is characterized by exceeding the amplitude value of the speech signal by its threshold value selected by the second inputs of block 2 of the comparison. In that

If the counter 9 is reset, the And 12 element is closed at its second input, and therefore the second trigger 11 is transferred to the zero state, which in turn closes the key 4 and opens the key 3. Thus, the additional channel is turned off, and the main one is connected to the signal combining unit 5.

Claims (1)

Invention Formula A device for detecting pauses of an eye, containing a delay line, the editor A.Sabo Compiled by O. Geller Tehred O. Sopko Order 2783/57 Circulation 624 Subscription VNIIPI. USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, Projecto st., 4 f5 2332904 the first comparator unit, breakthrough {i is the second keys, the outputs of which are connected to the corresponding inputs of the signal combining unit, the first with the inputs of the first and second keys being the inputs of the corresponding and secondary channels, And with the aim that, in order to improve the accuracy of the Q pauses of speech, the analog-to-digital converter, the second comparison block, the first and second counters, two triggers, the AND element and the clock pulse generator, whose output connected to clock inputs of the first and second blocks for comparison, to the clock inputs of the first and second counters and to the clock input of the analog-to-digital converter, the outputs of which are connected to the first signal HbLM inputs of the first and second comparison units, and to the inputs of the delay line whose outputs are connected to the second signal inputs of the second comparison unit, the first output of which is connected to the counting input of the first counter, the output of which is connected to the single input of the first trigger, the output of which is connected to the first input of the AND element, the second input of which is the subkey to the first output ode to the first comparison unit and to the counting input of the second counter, the installation input of which is connected to the second output of the first comparison unit and to the installation input 20 25 thirty the house of the second trigger, the unit input of which is connected to the outputs of the element I and the second counter, the second spin of the second comparison unit is connected to the installation inputs of the first counter and the first trigger, the inverse and unit outputs of the second trigger are connected to the second inputs of the first and second keys, respectively the signal input of the analog-digital converter is connected to the first input of the first key, and the second signal input of the first comparison unit is the threshold input of the device. Proofreader - E. Sirohkan