SU1533021A2 - Mutiple-frequency receiver - Google Patents

Abstract

The invention relates to communication technology. The purpose of the invention is to increase the noise immunity from phase interference. The device contains a multiplexer 1, a comparator 2, a step-voltage generator 3, a pulse counter 4, a control trigger 5, a decoder 8, two elements AND 9.10, two blocks 13, 15 matches, a register 17 of memory, a block of 19 keys, an element OR 21, two clock buses 22, 23, communication channels 26.1-26.K. The goal is achieved by introducing into the control trigger device 6, a countable trigger 7, two AND 11.12 elements and two clock buses 24.25. A certain combination of these elements and their connection with the other elements of the device changed the principle of its operation in terms of controlling the connection of channels with the required level to the output of the device. Reducing the number of switching channels with the desired level to the output device. A reduction in the number of channel switching increases the reliability of the transmission, since the probability of its distortion is therefore minimized. 1 il.

Description

WITH

with:

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the voltage, the estimator 4 pulses, the control trigger, the decoder 8, two elements OF, 10, two blocks 13, 15 matches, memory register 17, block 19 keys, element OR 21, two clock buses 22, 23, channels 26.1 - 26.K communication. The goal is achieved by introducing into the device control r trigger 6, a countable trigger 7, two JQ as the probability of its distortion by this

busses 2k, 25. Determined from these elements and their connections by r-c o rm device elements changed the principle of its operation in terms of controlling the connection of channels with the required level to the output of the device. The reduction in the number of channel switching increases the reliability of the transmission, so

Elements And 11, 12 and two clock

reason minimized. 1 il.

The invention relates to communication technology and can be used to automatically search for a communication channel with a maximum signal level and is additional to the main aut. St. № 12250 8.

The aim of the invention is to increase the noise immunity from phase interference.

The drawing shows a .d block diagram of a device for automatically searching for a communication channel.

The soder i multiplexer 1 device, comparator 2, step voltage generator 3, pulse counter k, control trigger 5, additional control trigger 6, counting trigger 7 decoder 8, first, second, tpety and fourth elements And 9,10,11 and 12, a pee coincidence block 13 including K first coincidence elements 1, a second coincidence block 15 including K second coincidence elements 16, a memory register 17 including K triggers 18, a key block 19 consisting of K keys 20, an OR element 21, the first, third, and fourth clock 22, 23, and 5, to Nala 26 bonds.

The device operates as follows OR.

The determination of the communication channel through which the signal with the maximum amplitude is received is made by comparing the signals coming from channels 26.1-26. To communication through multiplexer 1 to the first input of the comparator 2 with a step voltage coming from a generator 3 of step voltage to the second the input of the comparator 2. At the same time, the connection of channels 26.1-26, To the connection to the output of multiplexer 1 and the formation of the step voltage is synchronous,

as the probability of its distortion by this

busses 2k, 25. Determined from these elements and their connections by rc with components of devices, they changed the principle of its operation in terms of controlling the connection of channels with the required level to the output of the device. Reducing the number of channel switches increases the reliability of the transmission, so

reason minimized. 1 il.

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and the connection of channels 26.1-26. To the connection to the element OR 21 at the time of determining the channel that has the signal with the highest amplitude.

This happens next. A continuous sequence of clock pulses TI 1 is fed to the input of the pulse counter k on the first clock bus 22, as a result of which a sequence of n-bit binary codes is formed at its outputs. These codes are sent to the control inputs of multiplexer 1 and the inputs of the decoder 8. Channels 26.1-26 are connected to the second inputs of multiplexer 1. The connection, the number of which is K, is related to the n-code width of the input to the control inputs of multiplexer 1 by the relation .

Consequently, from the output of multiplexer 1 to the input of the comparator 2 will receive a signal from the channel, the number of which corresponds to the code generated in the given clock interval at the outputs of the counter k. A step voltage is supplied to the second input of the comparator from the output of generator 3. Moreover, when each overflow pulse arrives from the control output of counter k to the input of generator 3 (provided that the fourth E12 is open), the voltage at the output of the last decreases by one step .

The initial state of the generator 3, in which it is set by a pulse arriving from the first element I9 at the second input, corresponds to the maximum output voltage. The step size of the step voltage is determined by the given accuracy of determining the channel with the maximum signal in terms of magnitude, and

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steps - the amplitude sign of the input signals.

The duration of one stage is equal to K clock intervals of the TECs. Therefore, during the time of one stage, all codes from 0 to K are sequentially generated at the output of the counter, and signals from all K of communication channels 26 are sequentially received at the first input of comparator 2 through multiplexer 1. It will not be compared with any of these signals, the signal at the output of the generator 3 and, accordingly, at the second input of the comparator 2 will decrease by one step, and the counter k will begin a new cycle of generating codes connecting the signals from the output channels through multiplexer 1 to the first input comparator 2.

As soon as in one of the cycles of the counter C, the signal received from multiplexer 1 at the first input of comparator 2 is compared with the voltage currently set at the second input of comparator 2, a pulse will be generated at its output and will switch the control trigger 5 In state 1. In this case, the first element E9 and the second element E10 are opened, because the additional inputs of these elements receive an enable level from the additional control trigger 6.

At the same time, at the output of the second UI element, a pulse is formed that gates the elements of the match I Tl-l tK of block 13 via the second inputs. Only one of these elements, namely the one that receives the resolving level from the decoder, will be opened at the first input 8. Moreover, the number of this output will correspond to the binary code received in the given clock interval from the counter t, and hence the channel number, the signal from which in the given clock interval goes through multiplexer 1 to the first input of the comparator 2.

Suppose that at this moment an element of coincidence X.1 will be opened. Then the pulse from the output of the second element E10 will be sent to the first input of the trigger 18.1 of the register 17 of the memory and set it to state 1. At the same time, the first input opens the key 20.1 of the block 19 to the signal coming from the communication channel 26 to the second input

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key 20.1, through the element OR 21 will go to the output device. Through the clock interval of the input element I9, the second clock bus 23 will receive the clock pulse TI2. Since this element in the given clock interval is opened by the control signal from the output of the control trigger JQ Gera 5, TI2 will pass through it and gates the first inputs of the match elements 16.1-16.K of the block 15. The second inputs of these elements receive the control signals from the inverse of J5 of the decoder 8, therefore the element of coincidence 16.1 will be closed, and all other elements of coincidence 16.2-16. K will be opened through the second inputs. Consequently, the strobe pulse 20 from the output of the first element I9 will pass through all open elements of the match of block 15 and set all the triggers 18.2-18.

In this case, all the keys 20.2-20. They are closed by the second inputs and the signals from the communication channels 26 to their first inputs will not be output, and the signal will pass only through the key 20.1. 30 In addition, the pulse from the output of the first element I9 goes to the second input of the generator 3 and sets it to the initial state, since the output will set the maximum voltage, after which a new channel search period is started, through which the signal with the maximum amplitude enters.

The signal from control trigger 5 also opens the third element I11, Q through which the TIZ clock pulse passes through the third clock bus 2k and sets additional control trigger 6 to state 1. At the same time, the enable level 5 is removed from the additional inputs and the second elements Thus, until the end of the cycle of operation of the counter k, the connection to the output of the device of another communication channel 26 Q is excluded. By a clock pulse TI4 arriving over the fourth clock bus 25, the control trigger 5 returns to its original state.

An overflow pulse from the control output of the counter (coincident in time with TI1) is additional — trigger 6 is reset. If the latter enters this state, then by

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Claims (1)

the counting input triggers the counting trigger 7, prohibiting the operation of the fourth element I12, i.e. the overflow pulse from meter A does not transfer the generator 3 to another step (downward) of the voltage. This ensures that only the filled channel, the signal of which has the highest amplitude, is connected to the output of the device. The counting trigger 7 returns to its initial state with clock pulses of the TEC. If the comparison on comparator 2 in the cycle of the counter k does not occur, then the counting trigger 7 does not work and the overflow pulse passes through the fourth element I12 and decreases the generator voltage 3 by a step. Device for automatic search of a communication channel by auth.St. 0 five 0 18 No. 12250 8, different in that, in order to increase, ome, o,: protection against phase interference, a third connected element AND is introduced in series, an additional control trigger, the inverse output of which is also connected to the clock input of the input counting trigger and additional inputs of the first and second elements And, the fourth element And, the second input of which is connected to the inverse output of the counting trigger, the third and fourth clock tires connected respectively with the combined second input of the third element And and the input ca countable trigger and reset input of the control flip-flop, and the output pulse counter overflow is connected to the reset input of the additional control and trigger via the fourth AND gate - to the second input of the generator voltage stepwise.