SU1481907A1 - Device for measuring error factor - Google Patents

Abstract

THE INVENTION IS RELATED TO TELECOMMUNICATION, AND FOR THE TRANSMISSION OF DISCRETE INFORMATION. OBJECTIVE OF THE INVENTION - INCREASE ACCURACY MEASUREMENT. THE DEVICE CONTAINS A PHASE BLOCK 1, A COUNTER 2 TIME, A BLOCK 3 A CYCLE SYNCHRONIZATION AND ISOLATION OF ERRORS AND A COUNTER 4 ERRORS. PURPOSE is to be achieved by introducing into the unit the KEYS 5-7, the PANEL 8 COUNTING OF TEMPORARY INTERVALS AND DEVICE CONTROL. DEPENDING ON THE SIGNAL "0" OR "1" THE DEVICE WORKS IN TWO MODES: MODE 1-CONTINUOUS, MODE P-PACKET. MODE P IS INCLUDED WHEN THE INFORMATION SIGNAL IS SUBJECT TO PACKETS (IN MULTI-STATION ACCESS SYSTEMS WITH TEMPORARY SEAL). 1 IL.

Description

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The invention relates to telecommunications, namely to the transmission of discrete information, and can be used to measure the error rate in systems for transmitting discrete information and, in particular, in systems with a continuous information signal and in multi-access systems with time multiplexing.

The purpose of the invention is to increase the accuracy of measurement

The drawing shows a block diagram of a device for measuring the error rate.

The device contains a phasing unit 1, a counter 2 times, a block 3 of frame synchronization and error isolation, a counter 4 errors, keys 5 - /, counter 8, a decoder 9 with a lock, a decoder 10, inverters 11 and 12 and a differentiating element 13 "

The keys 5-7, the counter 8, the decoders 9 and 10, the inverters 11 and 12, and the differentiating element 13 perform the operation of counting time, intervals, and device control.

The device works as follows 067 at once.

Depending on the signal O or H1, the device operates in two modes. The first mode is continuous. When it at the third input of the device, they give a signal O. As a result, the key 6 is closed, therefore from the output of the inverter 11 to the inputs of the counter 2 are time and the 4 error counters the signal 1 is received, which allows them to work. allocates a clock signal that arrives at the counter 2 times and block 3. In the latter, cycle synchronization and verification of observance of the binary symbols tracking law in the incoming information signal is performed. When cyclic synchronization is established, a pulse appears at the output of block 3, which is fed to the input of key 5. When a violation of the law of binary symbols appears in the information signal, pulses appear at the first output of block 3. These pulses, corresponding to errors, are counted in the counter 4 mistakes. At the same time, the counter 2 times by counting the pulses of the clock signal measures the measurement time. When time ends, counter 2 outputs a signal to the error counter 4, which generates a signal corresponding to the error ratio at the device output.

The second mode is batch. This mode is activated when the information signal follows the packets in time-multiplexed access systems. In batch mode, a signal is sent to the third input of the device. As a result,

5, the key 6 is opened and the signal at the output of the inverter 11 is an inverted signal from the output of the decoder 9. Let the decoders 9 and 10 have at the initial moment of time.

0 are on the outputs 1. Then at the output of the inverter 11 there is a Signal 1st from the output of the decoder 10 opens the key 5 and through the inverter 12 closes the key 7 o

5 The pulses from the output of block 3 pass through the differentiating element 3, which forms a short pulse from it to set the counter 8 to the initial state. Due to

0 this, at the outputs of the decoder 9 and 10, the signals O are set. At the output of the inverter 11 a signal is generated, the key 5 closes and thus prohibits the repeated installation of the counter 8.

Through inverter 12 opens

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key 7; The pulses arriving at the second input of the device pass through the key 7 to the information input of counter 8. When a specified number 8 appears at the outputs of the counter 8, the decoder 9 is activated and blocked so that the signal 1 is kept at its output until a new cycle .

5 This signal, passage through key 6 and inverter 11, stops the operation of counters 2 and 4. Counter 8 at this time continues to count until a code appears on its outputs,

0 corresponding to the code of the decoder 10. As soon as this signal occurs, 1m from the output of the decoder 10 opens the key 5 and closes the key 7 through the inverter 12. The counting stops. Interval 5 current time during which the inverter 11 has at the output signal 1 corresponds to the processing of one packet of the information signal. With rto5

dulling the new packet, the cycle is repeated.

Claims (1)

Invention Formula A device for measuring the error rate, comprising a counter, a time and a serially connected phasing unit, the output of which is connected to the first input of the time counter, a frame synchronization and error extraction unit and an error counter, the output of which is the output of the device whose input is the input of the phasing unit, which is combined with another input of the frame alignment block and error highlighting, is distinguished, i.e., by the fact that, in order to increase the measurement accuracy, the first key connected in series is entered, Fferen819076 curing cement, counter, decoder with blocking, second key and first inverter, the output of which is 5 keys to the first time counter input and another input of the error counter serially connected decoder, the second inverter and the third key whose output is connected to counting 10 to the input of the counter, and the second input is the second input of the device, the third input of which is another input of the second key, the outputs of the counter are connected to the corresponding inputs 15 of the decoder, the output of which is connected to the first input of the first key, the second input of which is connected to a different output of the frame synchronization unit and the selection of errors, the output A time counter 20 is connected to the third input of the error counter.