SU760462A1 - Discrete channel monitoring device - Google Patents

Description

The invention relates to telecommunications.

A device for monitoring discrete channels is known, which contains an error analyzer, a pulse-shaper. owls, delay element, block matches, the first, second and third keys, the first, second, third and fourth counters, and the registration unit [1].

However, the known device for monitoring discrete channels does not have the necessary accuracy and short monitoring time.

The purpose of the invention is to improve the accuracy and reduce the time control.

To do this, a device for monitoring discrete channels containing / error analyzer, pulse shaper, delay element, coincidence unit, first, second, and third keys, first, second, third, and fourth counters and a registration unit are entered into the interval sensor, the first and second elements OR and η elements AND by the number of outputs of the third counter, while the first output of the error analyzer is connected to the combined first inputs of the first and second keys, the outputs of which are through the first and second counts2

 Cheeky. Connected respectively to the first and second inputs of the registration unit, the output of which is connected to the combined control inputs

5 of the first and second counters, the second output of the analyzer oibib is connected to the signal input of the third counter, each output of which through the corresponding element I is connected to the corresponding signal input of the fourth counter, the outputs of which are connected to the corresponding. To the corresponding inputs of the coincidence block, the output of which is connected to the clock input of the fourth counter through the serially connected third key and OR element, the control input of which, combined with the second inputs of the first and second keys and the first input of the second OR element, is given. drove "Receive Code", and the first exit

The interval sensor is connected to the third input of the second key and, to the second input of the third key, the output and the third

25 whose input is connected respectively to the third input of the first key and the combined second output of the interval sensor and the input of the pulse shaper, the output of which is connected to

30 combined second inputs η elements3

And the input of the delay element, the output of which is connected to the combined inputs of the first OR element and the second OR element, the output of which is connected to the control input of the third counter * · U \ '. · -. FIG. ί shows the structural circuit of the proposed device; figure 2 - diagrams explaining the operation of the device.

A device for monitoring discrete .7 channels contains error analyzer 1, key 2, element OR 3, unit 4 matches, counter 5, elements AND 6, counter. 7, Element OR 8, sensor 9 inter. shaft, driver 10 pulses, the delay element 11, the keys 12 and 13, 15

counters 14 and 15, block 16 registration.

The device works as follows: ZOM.

In the counter 7 during the interval T (FIG. 2a) of the interval sensor 9, the errors (for example, K errors) are accumulated (FIG. 2d). At the end of interval T transfer pulse formed by the pulse shaper 10 (Figure 26) .oshibki from the counter 7 via the AND b pereno- _{February 5} are carried to the counter 5 (2E) in the reverse code, i.e. at. counter 5 enters η K -1) osybka. The delayed transfer pulse generated by the delay element 11, through the element OR 3, is additionally recorded in the __ tick 5 unit, i.e. in the counter 5 is the number (p - k) (fig.2e). At the same time, the delayed transfer pulse ^ resets counter 7 through the element * OR 8, and counter 7 during the next interval T remembers the incoming errors from the error analyzer 1 again. During the negative pulse of the interval T (Fig. 2a), the key 2 turns out to be closed and the number (η - k) is 40

stored in the counter 5. A positive impulse interval T opens the key 2, the input of which receives the clock frequency from the sensor 9 intervals. ‘DG

The pulses of the clock frequency through the key 2 and the element OR 3 fill the counter 5 (the counter 5 will receive H (n -k) = to the pulses until it is charged). These K pulses from the output of the key 2 are transmitted through the key 12 to the counter 14.

When the counter is full (resetting the counter 5), the block 4 is triggered, closing key 2, i.e. the arrival of pulses in the counter 5, and through the key 12 intake of pulses. at _ . "

counter 14 is stopped “by the next’ pulse of the next interval ’t is carried out in the return code; errors from counter 7 to counter 5 and

‘T.d. . 450

At the beginning of control, i.e. signal

phasing produced by the analyzer 1 errors, open the keys 12 th:

'1’3', t-e. ”Counter inputs open '

14 and counter 15. Counter 15 counts

760462

the duration of the monitoring cycle (pulses of the clock frequency and the sensor 9 intervals through the key 13 are fed to the counter 15). The results of monitoring and recording the end of the measuring interval are carried out by the registration unit 16, which resets the counter 14 and the counter 15, starting a new channel test cycle.

When the “Receive code” signal arrives, the inputs of counter 14 and counter 15 are locked through keys 12 and 13. At the same time, the memory of errors received during the decoding of the code accumulated in counter 5 is reset ₍ and counter 7 through the OR 8 element when the key is removed, the keys 12 and 13 are locked, and the monitoring continues until the end of the measurement interval.

Suppose, for example, for the period T in the counter 7 did not receive a single error, i.e. the number 00000 (K = 0) was recorded. Then the number 11111 (that is, 31) will be transferred to counter 5 in the return code. With the delayed transfer pulse, the unit is added to the counter 5 through the element OR 3, and the counter 5 records the number 00000, (resetting the counter), over which the block 4 matches will close the key 2, and no error will enter the counter 14.

Technical and economic efficiency of the device for monitoring discrete channels is to improve the accuracy and reduce the monitoring time.

Claims (1)

Claim A device for monitoring discrete channels containing an error analyzer, a pulse shaper, a delay element, a holder, a coincidence unit, the first, second and third keys, the first, second, third, and fourth counters and the registration unit, respectively, so that, in order to increase the accuracy and reduce the monitoring time, the interval sensor, the first and second elements OR and V ”of the AND elements are introduced according to the number of outputs of the third counter, the first output of the error analyzer connected to the combined first inputs of the first and second keys, the outputs which with responsibly through the first and second counters are connected to the first and second inputs of the _registration unit, which is connected to the combined control inputs of the first and second counters, the second output of the error analyzer is connected to the signal input of the third counter, each output of which is connected to the corresponding signal input of the fourth counter whose outputs are connected to the corresponding inputs 760462 block of coincidence, the output of which is through the third connected in series; the key and the first element OR are connected, to the clock input of the fourth "counter", to the control input of the first, combined by the first inputs of the first and second keys, the first ³ the input of the second element OR, the signal "Receive code" is given, and the first output of the interval sensor is connected to the third input of the second key and the second input of the third key, the output and the third input of which are connected respectively to the third input of the first key and the combined second output of the Interval sensor pulses, the output of which is connected to the combined second inputs η of the AND elements and the input of the delay element, the output of which is connected to the combined second inputs of the first OR element and the second OR element, whose output By connecting the control input of the third counter.