SU1307596A1 - Device for detecting pauses in speech - Google Patents

Abstract

The invention relates to telecommunications and provides improved detection accuracy. The device contains the shift register 2, the keys 3,4, 5, counters (MF) 6, 7, 10, the element OR 8, the D-flip-flop 9, the decoder 11, the inverter 12, the information channel 16 containing the key 17, and the block 18 combining channels. The speech information in the form of PCM samples is received from information input 14 to shift register 2. Each PCM count is represented by a code pattern of K bits. The sampling frequency pulses are counted as MF 6 with a coefficient of. recalculation, which determines the observation interval. The transfer pulses from its output are zeroed MF 7, which counts the pulses coming from the key 4. The recalculation of the MF 7 is determined from the conditions so that the device does not react to noise pulses and reliably extracts speech fragments starting with explosive sounds. The transfer pulse of the MF 7 sets the B-trigger-er 9 to one, and the MF 10 sets it to zero. The D-flip-flop signal 9 permits the transmission of the HF-6 transmission pulses through the key 5 at the MF-10. The MF-10 is designed to delay the release of the speech channel 16 after the subscriber switches from conversation to silence. 1 il. sl CAD o SL CO 05

Description

eleven

The invention relates to telecommunications and can be used to detect speech pauses, in particular, in speech signal compression systems with additional information.

The purpose of the invention is to increase the reliability of speech pauses.

The drawing shows an electrical block diagram of a device for detecting pauses of speech with an information channel and a channel combination unit.

The device 1 for detecting speech pauses contains a shift register 2, the first 3, the second 4. and the third 5 keys, the first 6 and second 7 counters, e; the OR 8, D-flip-flop 9, the third counter 10, the decoder 11 and the inverter 12. In addition, the drawing shows the input 13 of clock pulses, the information input 14, the input 15 of the sampling signal, as well as the information channel 16 containing the key 17, and the channel combining unit 18.

A device for detecting speech pauses works in the following; 1 gm fashion.

Information from an external speech processor is fed as NKM signal samples in a sequential code to information input 14, with each PCM signal being represented by a code pattern of K bits.

With the most significant bit, the code combination of the sample carries information about the sign of the speech signal, while the other bits characterize its level. Information is written to the 2 Shift register with the frequency of the clock signal, which is fed to the input 13. As in silence mode, due to the background noise and other causes, occurrences of units in the four digits of code combinations are possible, the information to decide the transition of the subscriber to the active state is the appearance of units in the three higher bits of the code combinations of samples. For sampling, the additional outputs of shift register 2, corresponding to the three most significant bits of the speech signal, are connected to the OR element 8. The shift register capacity 2 is numerically equal to the K-N product, where N is the number of samples written to the register. Dp reliable allocation of the shortest phonemes corresponding to explosive sounds to.

0

15

25

075962

p, b, d, etc., whose duration lies in the range of 20-25 ms, the parameter N is chosen equal to 320, which corresponds to writing to the information shift register 2 on the 40-ms speech segment at the sampling frequency S kHz and K 8 At the same time, a delay of 40 ms does not significantly affect the quality of the dialogue. The sampling frequency pulses are fed to the input 15; the moments of their arrival correspond to the moments of recording in the register 2 of the shift of the next PCM-signal. The sampling rate pulses are counted by the first counter 6 with a conversion factor of N 320, which determines the observation interval (the time during which the information in the shift register 2 is completely replaced). The transfer pulses at the output of the first counter 6 appear with a period of 40 ms and the settings are made in O of the second counter 7, which is intended for counting the pulses coming from the output of the second key 4, which are formed at the instants determined by the sampling signal, if there is an enable signal from the output of the elec NTA

 O or 8. The permissive signal occurs when there is a unit in at least one of the three highest PCM level reference bits. The recalculation factor of the second counter 7 selects the course from the fact that the speech pause detection device does not have to respond to separate short (up to 10 ms) noise pulses and, moreover, it must reliably pick off the beginning

40 words and separate semantic fragments of speech, beginning with explosive sounds, especially critical to the accuracy of the analysis.

Assuming that separately

If the 45th sound impulse pulse has all the samples of a large level, then in 10 ms, a maximum of 80 sampling frequency pulses are fed through the second key 4 to the input of the second counter 7. Therefore, the conversion factor of the second counter 7 is chosen to be 80. Such a coefficient ensures the cutting out of short stand-alone noise im-: pulses, and also allows you to reliably

55 classify the beginning of words and semantic fragments of speech, even in the case of the shortest phonemes. If the subscriber is silent, then the second counter 7 does not have time to count the required number

Pulses and vertically are set to O by a transfer pulse from the output of the first counter 6 at the end of each observation interval.

During the transition, the subscriber is in active state, the second counter 7 for the duration of the observation interval (40 ms) has time to count the required number of pulses and generates in its

changed to the opposite, which leads to the opening of the first key and locking the key 17.

Claims (1)

Formula iso p and e and the output of the transfer pulse, which is tired of this signal from the output of the decoder 11 Pushes the D-flip-flop 9 on the entrance to the unit my state, and the third counter 10 - to the zero state. The signal from the direct output of the D-flip-flop 9 allows the transfer of the pulses of the first counter to pass through the third key 5 to the input of the third counter 10. At the same time, the transfer pulse of the second counter 7 periodically sets the third counter 10 to the zero state, the third counter 20 10 plays the role of an inertial element, which is designed to delay the release of the speech channel by 160-200 ms after the subscriber transitions from conversation to silence. The transfer pulses of the first 25 of the counter 6 follow with a period of 40 ms, therefore, to ensure a delay in the release of the main channel of 160-200 ms, the conversion factor of the third counter 10 is set to 4-5. ZO When the subscriber goes from talking to silence, D-flip-flop 9 is in a single state, which ensures the passage of pulses from the output of the third key 5 to the input of the third counter 10, which counts the specified number of pulses. In this case, a signal appears at the output of the decoder 11, which sets the D-flip-flop 9 to the zero state. The third key 5 is closed, jg which ensures the preservation of the state of the third counter 10, and consequently, the preservation of the corresponding signal at the output of the decoder 11. Thus, after 160-200 ms after 5 35 A device for detecting speech pauses, containing successively connected shift register and first key, first and second counters, an investor, second and third keys, characterized in that, in order to increase the reliability of the detection, sequentially connected third counters are entered into it, which through the third key is connected to the output of the first counter, combined with the installation input in O of the second counter, the decoder, whose output is connected to the input of the inverter and to the control input of the first key, the IL element whose inputs are connected the shift register outputs, and the output is connected to the signal input of the second counter via the second key, and the D-flip-flop, the second input of which is connected to the output of the second counter, combined with the installation input of the third counter O, and the output connected to the control input of the third key, while the control input of the second key is integrated by the information input of the first counter and is the input of the discretization signal. Editor A. Ogar Order 1642/56 Compiled by E. Borisov Tehred A. Kravchuk Proofreader T. Kolb Circulation 639 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, st. Project, 4 964 as the subscriber becomes silent, the first key 3 is closed, and the key 17 is opened, which provides a connection to the output of block 18 combining information channel 16. When the subscriber transitions to the active state, D-flip-flop 9 is again set to one, and the third counter 10 is set to zero. With changed to the opposite, which leads to the opening of the first key 3 and locking the key 17. Formula iso p and e and 5 5 o g 5 five A device for detecting speech pauses, containing sequentially connected shift register and first key, first and second counters, inverter, second and third keys, characterized in that, in order to increase the detection accuracy, a third counter, which is input through a third the key is connected to the output of the first counter, combined with the installation input O of the second counter, the decoder, the output of which is connected to the input of the inverter and to the control input of the first key, the OR element whose inputs to are connected to the shift register outputs, and the output is connected to the signal input of the second counter via the second key, and a D-flip-flop, the second input of which is connected to the output of the second counter, combined with the installation input of the third counter, and the output connected to the control input of the third key In this case, the control input of the second key is combined with the information input of the first counter and is the input of the discretization signal.