SU1453612A1 - Receiver of frequency-manipulated signal - Google Patents

Abstract

This invention relates to radio. The purpose of the invention is to increase the noise immunity of the device. The device contains in-phase and quadrature channels and 2 signal processing, consisting of P-trigger 3 and 4, El-5 and 6, counters 7 and pulses, comparison blocks 9 and 10, formers P and 12 pulses and delay blocks 13 and 14, as well as e-mails EXCLUSIVE OR 15, 16, 21 and 22, a low-pass filter .17. Controlled by r-18, a phase shifter 19 and a clock synchronization unit 20. The device automatically adjusts the frequency - 8 to the average frequency of the received input frequency-manipulated signal. The decision on the quadrature components of the input signal, pa is taken from the difference frequency signal at the inputs of L-flip-flops 3 and 4, which are used as phases, mx detector in channels 1 and 2. This is done by strobing the output of the corresponding 5 fields; D-Triggers 3 and 4 are short and 4d; average frequency bands using elements 5 and 6, counting pulses with counters 7 and B, and comparing the number of accumulated pulses with a threshold using components 9 and 10 Then, using the ELIMINARY ISH ELECTOR (2, decoder vanie quadrature components of the two channels and for determining the value of the received symbol and eliminate the effect reverse operation. Further e-t ISKLK5CHAYU111EE SHI 22 gchityvaet predgduschey phase shift per clock period, I yl. 1L

Description

The invention relates to radio communications and can be used in apparatus for receiving frequency-manipulated signals,

The purpose of the invention is the invention.

The drawing shows a functional diagram of a device for receiving hourly-manipulated signal,

The device contains in-phase 1 and quadrature 2 signal processing channels, each of which respectively consists of D-flip-flops 3 and 4, elements 5 and 6, x-detectors 7 and 8 pulses, blocks 9 and 10 of comparison, shapers 11 and 2 pulses to delay blocks 13 and 14, the first 15 and second 16 elements EXCLUSIVE OR, filter 17 lower hours *

that _P controlled ge neratsr 18, phases o- rotator 1 9 _e block 20 clock synch- ronieation, and. third 21 and even the fourth 22 you are angry EXCLUSIVE OR, Devices your work ¹ a t e g d: a d u ι-οπι and m

way.

The received frequency-manipulated signal arrives at the information inputs of the D-triggers 3 and 4, which are used as phase detectors and together with the elements 15 and 16 EXCLUSIVE OR, a low-pass filter 17 controlled by an oscillator 18, a phase shifter 19, performing a phase shift of 90 ° , and the clock synchronization unit 20 forms a modified Costas ring in which the frequency of the controlled oscillator 18 is automatically tuned to the average frequency of the received signal. The decision on the values of the quadrature components of the input signal is made according to the difference frequency signal at the P-triggers 3 and 4 inputs in each signal processing channel by strobing the output of the corresponding trigger with short middle-frequency pulses using elements I 5 and 6, counting the gating pulses by counters 7 and 8 pulses and comparing the number of accumulated pulses with a threshold using blocks 9 and 10 of the comparison. In this: in the case of gating pulses pass to the output of the And 5 (6) element, if the output of the D-trigger 3 (4) ’is the Log level. 1 ”, and does not pass otherwise. The capacity of each counter and 8 cells should be at least 2n, and the comparison threshold should be equal to n, where η is the integer part of the ratio of the average frequency to the clock. The clock synchronization unit 2.0 extracts the half-clock frequency signal from the video signal present at the output of the EXCLUSIVE RESEARCH element 15. In this case, the frequency is doubled, as a result of which the spectrum of the received signal will contain a discrete component of the clock frequency. The clock signal is allocated by the auto-tuning system and, after dividing by 2, is fed to the block outputs, while the signal at the first output is phase-shifted 90 ° relative to the signal at the third output.

Decisions are made in channels 1 and 2 of the signal processing at the moments determined by the positive edges of the signals present at the second and first outputs of the clock synchronization unit 20, respectively, while the decision moments in these channels shift ’in time relative to each other by one clock interval.

Information at the output of comparison blocks 9 (10) is established at the time of making a decision and is stored until the next decision making moment. The delay unit 13 (14) serves to ensure that the setting of the output value of the comparison unit 9 (16) precedes the zeroing of the counter 7 (8).

With the EXCLUSIVE OR gate 21 decodes the quadrature components of the channels 1 and 2 of the signal processing to determine the value of the received symbol, while eliminating the effect of reverse operation, which may be caused by intrinsic Kolno Costas uncertainty 180 ^th phase medium frequency signal at the output of controlled oscillator 18.

Using the EXCLUSIVE OR 22 element, the phase incursion of the previous clock interval is taken into account.

Claims (1)

Claim A device for receiving a frequency-manipulated signal containing common-mode and quadrature signal processing channels, the information inputs of which are combined and are the input of the device, and the first outputs are connected to the inputs of the first EXCLUSIVE OR element, the output of which is connected to the input of the clock synchronization unit, the first and second outputs of which are connected to clock inputs, respectively, of the quadrature and in-phase signal processing channels, and the third output is connected to the first input of the second EXCLUSIVE OR element, the second whose input is connected to the input of the clock synchronization unit, and the ed output is s. low-pass filter input, the output of which through a controlled oscillator is connected to the input of the phase shifter, the input and output of which are, respectively, the reference inputs _of the quadrature and in-phase signal processing channels, the information outputs of which are connected to the inputs of the third EXCLUSIVE OR element, the output of which is connected to the first input of the fourth element is EXCLUSIVE OR: the output of which is the output of the device, and the second input is connected to the first output of the clock synchronization unit, while in-phase and quadrature second processing channels comprise a D-trigger, the informa-. The sync and sync input of which is the information and reference inputs of the inphase and quadrature signal processing channels, characterized in that, in order to increase the noise immunity, a pulse shaper, a delay unit and a series-connected And element, a pulse counter and a comparison unit are introduced into the common mode and quadrature signal processing channels , the output of which is the information output of the in-phase and quadrature channels of signal processing, as well as the input is a clock input of the in-phase and quadrature channels of signal processing and is connected to the input of the delay unit, the output of which is connected to the second input of the pulse counter, the input of the pulse shaper is connected to the clock input of the D-trigger, and the output is connected to the first input of the element And, the second input of which is connected with the output of the D-trigger, which is the first output of the in-phase and quadrature processing channels 30 signals.