RU2364022C2 - Device of broadband signal search - Google Patents

Abstract

FIELD: communication facilities.

SUBSTANCE: invention concerns radio technology and can be applied in design of radio communication, radio navigation, control schemes using broadband signals. Effect is achieved by more complete check by differentiating indicators of useful signal and structural interference. Device of broadband signal search includes line part (1), transformable matched filtre (2), k detectors (3₁-3_k), k power units with threshold (4₁-4_k), k keys (5₁-5_k), k logical NOT elements (6₁-6_k), two logical OR element schemes (7 and 8), key notifying of the decision of signal detection (9), trigger (10), counter (11), clock-pulse oscillator (12), channel switch control unit (13) and timers unit (14).

EFFECT: reduced probability of false synchronisation to strong structural interference.

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Description

The proposed device relates to the field of radio engineering and can find application in the construction of radio communication systems, radio navigation, control, using broadband signals.

Known devices for searching for broadband signals (see AS No. 1003372 H04L 7/02, 1981; No. 809619 H04L 7/02, 1979), which have a common disadvantage, which consists in low noise immunity of the search for broadband signals (SHPS) by delay, namely, in a high probability of synchronization of search devices for structural interference.

The closest in technical essence to the proposed is the device described in the book [1] on p.66-70, 195-199, 234-240, taken as a prototype.

Figure 1 shows a block diagram of a prototype, which shows the following notation:

1 - linear part;

2 - matched filter;

3 ₁ - detector;

4 ₁ - block comparison with the threshold;

21 - preliminary filter;

22 - delay line;

23.1-23.k - the first, ..., k-th attenuators;

24.1-24.k - the first, ..., k-th phase shifters;

25 - adder.

The prototype device contains a series-connected linear part 1, the input of which is the input of the device, and a matched filter 2, which contains a series-connected pre-filter 21 and a delay line 22, the outputs of which are connected respectively to the inputs from the second to the k-th attenuator 23.2-23.k the outputs of which are connected respectively to the inputs from the second to the k-th phase shifter 24.2-24.k, the outputs of which are connected to the (k-1) inputs of the adder 25, respectively; wherein the input of the delay line 22 through the first attenuator 23.1 and the first phase shifter 24.1 is connected to the first input of the adder 25, the output of which, which is also the output of the matched filter 2, is connected through the detector 3 ₁ to the input of the comparison unit with a threshold 4 ₁ , the output of which is the output of the device .

The prototype device operates as follows.

The signal from the input of the device through block 1 is fed to the input of block 2, where through the block 21 it is fed to the input of block 22. From the input of block 22 and from its outputs, the signal elements through the corresponding series-connected blocks 23.1-23.k and blocks 24.1-24.k arrive at the corresponding k inputs of block 25. In this case, the parameters of block 22, blocks 23.1-23.k and blocks 24.1-24.k are selected so that at the output of block 25 the signal elements are added in phase and give the value of the autocorrelation function of the useful signal, and at the output of block 3 _{1 there} will be an envelope value of the autocorrelation function AI (ACF) of the desired signal.

In the case when there is structural interference at the input of the device, then at the output of block 3 ₁ in this case there will be the envelope value of the mutual correlation function (CCF) of the signal and structural interference.

Thus, if only a useful signal arrives at the input of the device, then exceeding the threshold in block 4 ₁ leads to the correct decision on the presence of a useful signal, and the search stops. If at the input of the device there is a powerful structural interference, then exceeding the threshold in block 4 ₁ will lead to an erroneous decision to terminate the signal search.

An enlarged diagram of the prototype device is presented in figure 2, which shows the following notation:

1 - linear part;

2 - matched filter;

3 ₁ - detector;

4 ₁ - block comparison with the threshold.

The enlarged prototype contains a linear part 1 connected in series, the signal input of which is the input of the device, a matched filter 2, detector 3 ₁ and a comparison unit with a threshold 4 ₁ , the output of which is the output of the device.

An enlarged prototype works as follows.

The signal from the input of the device through block 1 enters the input of block 2, where it is matched by filtering. From the output of block 2, the signal goes to the input of block 3 ₁ , where it is detected, and then the envelope value is compared with the threshold in the block

4 ₁ . Since powerful structural noise can also be received at the input of the device, there can be a signal at the output of block 3 ₁ that will be accepted by block 4 ₁ as true.

The disadvantage of the prototype device is the low noise immunity when exposed to powerful structural interference.

To eliminate this drawback, a broadband signal search device containing a linear part connected in series, the signal input of which is the device input, a matched filter, a first detector and a first threshold comparison unit, according to the invention, k keys, k logical elements “NOT”, (k -1) detectors, (k-1) threshold comparison blocks, the first and second “OR” logic element cascades, clock generator, channel switching control unit, timer unit, counter, trigger, and cl yuch for filing a decision on signal detection, a control input connected to the output of the channel switching control unit is additionally introduced into the linear part; the matched filter is tunable, and the first and second control inputs are additionally introduced in it, and the first control input of the tunable matched filter is connected to the output of the second cascade of logic elements “OR”, as well as to the control inputs of the timer block, trigger and counter, the second control input tunable matched filter connected to the output of the first circuit of the cascades of logical elements "OR", the counting input of the counter, the signal input of the timer block and the signal input of the key for making a decision on detecting a signal whose output is connected to the signal input of a trigger, the output of which is connected to the control inputs of the first key and key for making a decision on detecting a signal; the output of the first comparison unit with a threshold is connected to the signal input of the first key, the output of which is connected to the first input of the first cascade of logical elements "OR", and through the first logical element "NOT", to the first input of the second circuit of cascades of logical elements "OR"; the input of the first detector is connected to the inputs of (k-1) detectors, the outputs of which through the corresponding (k-1) comparison blocks with a threshold are connected to the signal inputs of the corresponding (k-1) keys, the outputs of which are connected to the corresponding (k-1) inputs of the second “OR” logic element cascades, and through the corresponding (k-1) NOT logic elements — with corresponding (k-1) inputs of the first “OR” logic element cascades; m outputs of the timer block, where m = k-1, are connected to the control inputs of the corresponding (k-1) keys; the output of the counter, which is also the output of the device, is connected to the (k + 1) -th input of the second circuit of the cascades of logical elements “OR” and the control input of the channel switching control unit, the clock input of which is connected to the output of the clock generator.

Figure 3 shows a block diagram of the proposed device, which shows the following notation:

1 - linear part;

2 - tunable matched filter (PSF);

3 ₁ , 3 ₂ , ... 3 _k - first, second, ... k-th detectors;

4 ₁ , 4 _{2, ...} 4 _k - the first, second, ... k-th blocks of comparison with the threshold;

5 ₁ , 5 ₂ , ... 5 _k - first, second, ... k-th keys;

6 ₁ , 6 ₂ , ... 6 _k - the first, second, ... k-th logical elements “NOT”;

7 and 8 - the first and second circuits of cascades of logical elements "OR";

9 - a key for submitting a decision on signal detection;

10 - trigger;

11 counter;

12 - clock generator;

13 - channel switching control unit (BUPK);

14 is a block of timers.

The proposed device contains a linear part 1, the signal input of which is the input of the device, and the output of the linear part 1 is connected to the signal input of a tunable matched filter 2, the output of which is connected to the inputs from the first to the k-th detectors 3 ₁ -3 _k , the outputs of which are through the corresponding from the first to the k-th comparison blocks with a threshold of 4 ₁ -4 _{k are} connected to the signal inputs of the corresponding from the first to the k-th keys 5 ₁ -5 _k .

The output of the first key 5 _{1 is} connected to the first input of the first circuit of the cascades of logical elements "OR" 7, and through the first logical element "NOT" 6 ₁ is connected to the first input of the second circuit of the cascades of logical elements "OR" 8.

The outputs from the second to the kth keys 5 ₂ -5 _{k are} connected to the corresponding from the second to kth inputs of the second circuit of the cascades of logical elements "OR" 8, and through the corresponding from the second to kth logical elements "OR" 6 ₂ - 6 _k - with the corresponding from the second to k-th inputs of the first circuit of cascades of logical elements "OR" 7.

The output of the first circuit of the cascades of logical elements "OR" 7 is connected to the signal input of the block of timers 14, the second control input of the tunable matched filter 2, the counting input of the counter 11 and the signal input of the key to submit a decision on the detection of signal 9.

The output of the second circuit of the cascades of logical elements "OR" 8 is connected to the first control input of the tunable matched filter 2 and the control inputs of the block of timers 14, trigger 10 and counter 11, the output of which, which is also the output of the device, is connected to (k + 1) the input of the second circuit of the cascades of logical elements "OR" 8 and the control input of the channel switching control unit (BUPK) 13, the clock input of which is connected to the output of the clock generator 12, and the output of the BUPK 13 is connected to the control input of the linear part 1.

From the first to the mth outputs of the block of timers 14 are connected respectively to the control inputs from the second to the kth keys 5 ₂ -5 _k .

The proposed device operates as follows.

A signal, structural noise, or a mixture thereof may be input to the device.

Initially, blocks 2, 10, 11, and 14 are in the initial state, which can be further achieved by supplying a logical “unit” to the control input (“RST” input) of these blocks. In the initial state, the output of block 10 is a logical unit that is supplied to the control inputs of the first key 5 ₁ and key 9, as a result of which they are open in the initial state, which ensures the passage of the signal from the output of block 4 ₁ to the first input of block 7 and from the output block 7 to the signal input of block 10; while blocks 5 ₂ -5 _k will be closed.

Consider the case when only the useful signal comes from the input of the device to the signal input of block 1.

The signal search takes place in two stages.

At the first stage of the search, the device detects a signal. From the output of block 1, the signal enters the signal input of block 2, where it is matched by filtering. The filtered signal from the output of block 2 is fed to the inputs of blocks 3 ₁ -3 _k . From the output of block 3 _{1, the} value of the envelope of the ACF of the useful signal is fed to the input of block 4 ₁ , where it is compared with a threshold value U _{1 of the pores} determined by the probability of correct detection. If a signal is detected, the threshold value U _{1 then} will be exceeded, and the logical unit from the output of block 4 ₁ through block 5 ₁ will go to the first input of block 7, and from the output of block 6 _{1, the} logic zero will go to the first input of block 8.

As a result, the output of block 7 will be a logical unit signal, which means that the device at the first stage of the search made a decision to detect the signal. The logical unit from the output of block 7 will go to the signal input of key 9, the counting input of block 11, the signal input of block 14 and the second control input of block 2. Since in the initial state the key 9 is in the open state, the decision to detect the signal will go to the signal input block 10, which will lead to a change in its state, and a logical zero from the output of block 10 will go to the control inputs of blocks 5 ₁ and 9, which will lead to their closure.

At the second stage of the search, the device performs a cyclic search for structural interference in the detected signal. The logical unit from the output of block 7 is fed to the counting input of the block of timers 11, as well as to the second control input of block 2, which will lead to the restructuring of block 2 and provide the possibility of receiving an orthogonal signal. In addition, the logical unit from the output of block 7 is fed to the signal input of block 14, which will lead to its launch.

At the end of the time equal to the period of the signal that is being searched, a logical unit will be formed at the first output of block 14, which will go to the control input of the second key 5 ₂ , which will lead to its opening.

At the moment of opening the second key 5 _{2, a} logical signal will arrive at its signal input, which is the result of comparing the envelope of the VCF noise at the output of the second detector 3 ₂ with the threshold value U _{2 of the pores of} block 4 ₂ determined by the probability of a false alarm. If there is only a useful signal at the input of the device, the threshold value U _{2 of the pores} will not be exceeded, and from the output of block 4 ₂ through block 5 _{2 the} logic zero will arrive at the second input of block 8, and the logical output from block 6 ₂ will go to the second input of block 7 unit.

Next, the cycle of searching for structural interference in the detected signal will be repeated until 3 _k , 4 _k , 5 _k , 6 _k blocks are connected in series.

When k logical units arrive at the counting input of block 11, a logical unit is formed at its output, which will go to the output of the device, to the (k + 1) -th input of block 8, and also to the control input of block 13, as a result of which the device will be prepared for work on this channel. The appearance of the signal at the output of block 11 means - the signal is found and the search for the signal is finished.

If a mixture of a useful signal and powerful structural noise arrives at the first, signal input of block 1, then, as in the case of a useful signal, at the first stage of the search, the sum of the envelopes of the ACF signal and the VCF noise generated at the output of block 3 ₁ will exceed the threshold value U _{1 pore} , and from the output of block 4 ₁ through block 5 _{1, the} logical unit will go to the first input of block 7, and from the output of block 6 _{1, the} logic zero will go to the first input of block 8.

As a result, a logic unit signal appears at the output of block 7, which means that the device at the first stage of the search made a decision to detect the signal. Since in the initial state the key 9 is in the open state, the decision to detect the signal will go to the signal input of the trigger 10, which will lead to a change in the state at its output, and a logical zero from the output of the trigger 10 will go to the control inputs of the blocks 5 ₁ and 9, which will lead to their closure.

At the second stage of the search, the device performs a cyclic search for structural interference in the detected signal. The logical unit from the output of block 7 is fed to the counting input of block 11, as well as to the second control input of block 2, which will lead to the restructuring of block 2 and will provide the possibility of receiving an orthogonal signal. In addition, the logical unit from the output of block 7 is fed to the signal input of block 14, which will lead to its launch.

At the end of the time equal to the period of the found signal, a logical unit is formed at the first output of block 14, which will go to the control input of the second key 5 ₂ , which will lead to its opening.

At the moment of opening the second key 5 _{2, a} logical signal will come to its signal input, which is the result of comparing the envelope of the VCF noise at the output of the second detector 3 ₂ with the threshold voltage value U _{2 of the pores of} block 4 ₂ determined by the probability of a false alarm. If there is a useful signal at the input of the device and powerful structural noise, the threshold U _{2 pores} will be exceeded, and from the output of block 4 ₂ through block 5 _{2, the} logical unit will go to the second input of block 8, and from the output of block 6 ₂ to the second input of block 7 logical zero will arrive.

Next, the cycle of searching for structural interference in the detected signal will be repeated until 3 _k , 4 _k , 5 _k , 6 _k blocks are connected in series.

The logical unit from the output of block 8 will go to the first control input of block 2 and to the control inputs of blocks 10, 11 and 14, which will lead to their reset, as a result of which the device will return to its original state, that is, it will be ready to search for a useful signal, and search The desired signal will be continued on other channels.

If only a powerful structural noise arrives at the input of the device, then the threshold voltage values U _{1 pore} -U _{k pore} in the corresponding blocks 4 ₁ -4 _k will be exceeded, and the operation of the search device will be the same as in the case of receiving a signal with strong structural interference .

The functional diagram of tunable matched filter 2 is shown in figure 4, where the following notation is introduced:

21 - preliminary filter;

22 - delay line;

23.1-23.k - the first, ..., k-th attenuators;

24.1 ₁ -24.k ₁ - the first, ..., k-th phase shifters of the first group;

24.1 ₂ -24.k ₂ - the first, ..., k-th phase shifters of the second group;

25 - adder;

26.1 ₁ -26.k ₁ - the first, ..., k-th keys of the first group;

26.1 ₂ -26.k ₂ - the first, ..., k-th keys of the second group;

27 - address decoder;

28 - read-only memory (ROM).

The tunable matched filter (PSF) 2 contains a pre-filter 21 connected in series, the input of which is the signal input of the PSF 2, and a delay line 22, the input and (k-1) of the outputs of which are connected respectively to the inputs k of the attenuators 23.1-23.k, the outputs of which connected to the first signal inputs of the corresponding key pair of the first 26.l ₁ -26.k ₁ and second 26.1 ₂ -26.k ₂ groups connected together. The second control input of PSF 2 is the signal input of address decoder 27, and the first control input of PSF 2 is the control input of address decoder 27. The group of outputs of the address decoder 27 is connected via a bus to the group of inputs of ROM 28, which has 2k outputs connected to the control inputs of the corresponding k keys of the first group 26.1 ₁ -26.k ₁ and k keys of the second group 26.1 ₂ -26.k ₂ . The outputs of the k keys of the first group 26.1 ₁ -26.k _{1 are} connected to the inputs of the corresponding phase shifters of the first group 24.1 ₁ -24.k ₁ , the outputs of which are connected to the k inputs of the first group of the adder 25, respectively. The outputs of the k keys of the second group 26.1 ₂ -26.k _{2 are} connected to the inputs of the corresponding phase shifters of the second group 24.1 ₂ -24.k ₂ , the outputs of which are connected to the k inputs of the second group of the adder 25, respectively.

The output of the adder 25 is the output of the PSF 2.

PSF 2 works as follows.

The signal received at the input of PSF 2 through block 21 is fed to the input of block 22. From the input of block 22 and from its (k-1) outputs, the signal elements are supplied to the corresponding key pairs of the first 26.1 ₁ -26.k ₁ and the second 26.1 ₂ -26. k ₂ groups.

In the initial state, a logic zero is at the control input of block 27, and a binary number corresponding to the zero address is at the outputs of block 27. Upon receipt of the logical input of the block 27 k logical signals, the block 27 generates an address for the ROM 28, according to which 2k outputs of the ROM 28 will be a combination of logical ones and zeros, which will lead to the opening or closing of the corresponding keys 26.1 ₁ -26.k ₂ as a result, the signals from the corresponding blocks 23.1-23.k, changing in phase in the corresponding blocks 24.1 ₁ -24.k ₂ , pass to the corresponding inputs of the adder 25. The combination of control signals for the keys is selected so that PSF 2 is consistent ( optimal) to detect signal being generated. In block 25, the summation of all components of the useful signal occurs, the result of which is fed to the output of block 2.

Upon receipt of a logical unit at the signal input of block 27, the next combination of zeros and ones will be selected, which from the group of outputs of block 27 will go to the group of inputs of ROM 28. At 2k outputs of ROM 28, another combination of logical units and zeros will be formed, which will open or close the corresponding keys 26.1 ₁ -26.k ₂ , as a result of which the signals from the corresponding blocks 23.1-23.k, changing in phase in the corresponding blocks 24.1 ₁ -24.k ₂ , pass to the corresponding inputs of the adder 25. The combination of control signals for the keys is selected so that PSF 2 is consistent for a signal that is orthogonal to the detected one. In block 25, the summation of all components of the useful signal occurs, the result of which is fed to the output of block 2.

The technique for selecting the parameters of phase shifters and key combinations for constructing optimal filters is widely known and is given in [2].

The block diagram of the channel switching control unit 13 is shown in FIG. 5, where the following notation is introduced:

131 - trigger;

132 - fixed number counter;

133 - shaper;

134 - channel switch;

135 - the key;

136 - tunable generator.

The channel switching control unit (BUPK) 13 comprises a series-connected key 135, a fixed number counter 132, a shaper 133, a channel switch 134 and a tunable generator 136, the output of which is the output of the BUPK 13; and also contains a trigger 131, the input of which is also the control input of the BUPK 13, and the output of the trigger 131 is connected to the control input of the key 135, the signal input of which is also the clock input of the BUPK 13.

BUPK 13 works as follows.

In the initial state, the output of the trigger 131 is a logical unit that holds the public key 135, and the output of the counter of fixed numbers 132 is a logical zero.

If the search device has detected a useful signal, then the logical unit will go to the input of block 131 from the output of block 11 and transfer it to another state, and the logical zero signal from the output of block 131 will go to the control input of block 135, which will close it. Therefore, the clock pulses from block 12 will not come to block 132, and the channels will not switch, thereby securing the fixation of this channel.

Consider the processes occurring in block 13, in the presence of a mixture of a useful signal and powerful structural noise at the input of the device, as well as in the presence of structural noise alone.

From the output of block 11, a logical zero is supplied to the input of block 131, which means that its output will be a logical unit that keeps block 135 open. In this case, the clock pulses from the output of block 12 through block 135 arrive at a certain number of clock pulses in block 132. This number determined by the time during which the search device will detect the signal on this channel. When a predetermined number of clock pulses is received, for which block 132 is designed, a logical unit is generated at its output, upon receipt of which a logical pulse is generated in block 133, upon receipt of which a block is switched to another channel in block 134, and a signal is generated at its output, which starts block 136, where the tuning to a different frequency occurs.

Block 134 can be implemented as a conventional band switch, which are widely used in various types of radios, that is, this is a well-known problem solved by known methods.

Consider block 136, which is a tunable generator. The work of a tunable generator is that it changes its frequency when the corresponding signals arrive at its input. In particular, a tunable generator can be performed on a DDS class chip - a direct digital synthesizer. This can be based on the AD 9858 chip (Analog Devices) in a typical switching circuit.

The functional diagram of the block of timers 14 is shown in Fig.6, where the following notation is introduced:

141 - shift register;

142 ₁ , ... 142 _m - the first, ... m-th timers;

143 ₁ , ... 143 _m - the first, ... mth formers.

The block of timers 14 contains a shift register 141, m outputs of which (where m = k-1) are connected to the inputs of the corresponding m timers 142 ₁ -142 _m , the outputs of which are connected to the inputs of the corresponding m formers 143 ₁ -143 _m , the outputs of which are the corresponding outputs block of timers 14. The signal input of the shift register 141 is the signal input of the block of timers 14, and the reset input to the zero state of the shift register 141 is the control input of the block of timers 14.

The block of timers 14 operates as follows.

In the initial state, the outputs of block 141 are logical zeros, blocks 142 ₁ -142 _m are in the non-running state.

In the case of the arrival of the first logical unit at the signal input of block 14, the shift register 141 will be filled, which will lead to the start of the first timer 142 ₁ . Having completed, the first timer 142 ₁ will give a signal to the first shaper 143 ₁ , which at the first output of block 14 will form a logical unit and feed it to the control input of the second key 5 ₂ . Key 5 ₂ will open and pass the signal to the corresponding inputs of blocks 7 and 8 for making further decisions.

In the case of the arrival of the second logical unit at the signal input of block 14, blocks 142 ₂ and 143 _{1 will work} , and so on until the arrival of m units.

If m logical units arrive at the signal input of block 141, the shift register 141 will be filled, which will lead to the start of the m-th timer 142 _m . Having fulfilled, the timer 142 _m will give a signal to the shaper 143 _m , which will form a logical unit and send to the control input of the k-th key 5 _k , which will open and pass the signal to the corresponding inputs of blocks 7 and 8 for making a further decision.

In the event that a logical unit arrives from the output of block 8 to the control input of block 14, the shift register will be reset to zero, which will return block 14 to its initial state. Such a state is possible in cases: when a signal is found or when a powerful structural noise or a mixture of a useful signal and powerful structural noise arrives at the input of the receiver.

Detectors, keys, and threshold comparison blocks are widely used. A description of the structure and principles of constructing such flowcharts can be found, for example, in the book [3].

Block 12 can be made on the basis of various types of generators, for example, on the basis of a crystal oscillator shown in Fig. 4.5 p. 86-87 in the book [3], or on the basis of a blocking generator shown in Fig. 4.9 p. 94-96 in the book [3].

Schemes of cascades of logical elements "OR" are given in the book [4].

Thus, the introduction of additional blocks in the claimed device reduces the likelihood of false synchronization for powerful structural interference due to a more complete check on the distinguishing features of the useful signal from structural interference, resulting in improved search efficiency of broadband signals.

Information sources

1. Noise-like signals in information transmission systems / edited by Pestryakova VB - M .: Owls. Radio, 1973.

2. Varakin L.E. / Communication systems with noise-like signals. - M .: Radio and communications, 1985.

3. Mandle M. / 200 selected electronics circuits / trans. from English under the editorship of Yitzhoki Ya.S. - M .: Mir, 1980.

4. Analog and digital electronics (Full course): Textbook for high schools / Yu.F. Opadchiy, O. P. Gludkin, A. I. Gurov. Ed. O.P. Gludkina. - M .: Hot Line - Telecom, 2000. 768 p.: Ill. p. 710-719.

Claims (1)

A broadband signal search device containing a linear part, the signal input of which is the device input, a tunable matched filter, k detectors, k threshold comparison blocks, k keys, k logical elements, NOT, the first and second circuits of logical elements OR, a key for making a decision about signal detection, trigger, clock generator, channel switching control unit, timer unit and counter, the output of which is the output of the device, while the output of the linear part is connected to the signal input a tunable matched filter, the output of which is connected to the inputs of k detectors, the output of each of the detectors through a corresponding comparison unit with a threshold is connected to the signal input of the corresponding key, the output of the first key is connected to the first input of the first logic circuit OR, and through the first logical element NOT - with the first input of the second OR gate circuit, the outputs from the second to kth keys are connected to the corresponding from the second to kth inputs of the second OR circuit, and through the corresponding from the second to the k-th logic elements are NOT - with the corresponding from the second to k-th inputs of the first OR logic circuit, the output of the first OR circuit is connected to the signal input of the timer block, the second control input of the tunable matched filter, the counting input of the counter and the signal input of the key for making a decision on detecting the signal, the output of the second circuit of the OR logic elements is connected to the first control input of the tunable matched filter and the control inputs of the timer block igger and counter, the output of which is connected to the (k + 1) -th input of the second OR logic circuit and the control input of the channel switching control unit, the clock input of which is connected to the output of the clock pulse generator, and the output of the channel switching control unit is connected to the linear control input parts, from the first to the mth outputs of the timer block are connected to the control inputs from the second to the kth keys, and the signal of a logical unit arriving at the first control input of the tunable matched filter is If the reset signal is tuned for it, the tunable matched filter is matched for the detected signal if there is no logical unit signal at its second control input, the tunable matched filter is matched for the signal orthogonal to the detected one if a logical unit signal arrives at its second control input.

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