SU1164902A1 - Device for transmission and reception of binary information device for transmission and reception of binary information - Google Patents

Abstract

I. TRANSMISSION AND RECEIVING DEVICE FOR BINARY INFORMATION, containing serially connected clock generator and signal generator on the transmitting side, the outputs of which are connected to the inputs of the signal selector unit, and on the receiving side - the generator of signals copies, the outputs of which are connected to the inputs of the correlator unit, outputs which are connected to the inputs of a decisive unit, and the signal input of the signal copy generator is connected to the signal input of the correlator unit, the clock input of which, as well as the clock The first input of the decision block is connected to the first output of the clock signal input block, which is so that, in order to narrow the operating frequency band while simultaneously improving noise immunity, the binary information block is inserted on the transmitting side into clock bits the input of which is connected to the output of the clock signal generator i and the outputs from the control inputs of the signal selection unit, and on the receiving side the first and second inputs and the second output of the clock extraction unit are connected respectively to a signal input, a signal output, and a control input of the driver of copies of the signals. 2. The device according to claim 1, which is based on the fact that the signal conditioner is made in the form of two (L signal generators, clock inputs of which are connected to the synchronizer output, and the outputs are directly and through one delay line connected to the corresponding signal inputs of the switching unit, the outputs of which are the outputs of the signal conditioner, whose input is the input of another delay line, the input and output of which are connected to the control inputs of the switching unit. 3. The device according to claim 1, which is shorter Signal signals are made in the form of two filters, the outputs of which, directly and through ddney, the delay lines are connected to the same inputs / switching unit whose outputs are the outputs of the signal copy generator, the signal input whose signal output and control input are respectively

Description

Inputs "1" ltr, the output of one of the filters and the input of another delay line, the input and output of which are connected to other inputs of the switching unit.

4. The device according to claim 1, characterized in that the block for selecting clock signals is made in the form of serially connected per4902

1ltra, a mixer, a second filter, a limiter, a differentiating circuit and a rectifier, with the first and second inputs, the first and second outputs of the clock block, respectively, the input of the first filter and the second input of the mixer, the outputs of the limiter and the rectifier -1,

The invention relates to radio and can be used in devices for transmitting and receiving binary information.

A device for transmitting and receiving binary information is known, comprising a serially connected coding bpock, a transcoding unit and a phase modulator on the receiving side, and a phase meter, a phase difference calculator and a decoder J on the receiving side.

A disadvantage of the known device is its unstable operation due to the presence of reverse operation.

The closest to the present invention is a device for transmitting and receiving binary information, containing on the transmitting side serially connected clock generator and signal conditioner, whose inputs are connected to the inputs of the signal selection unit, and on the receiving side - signal copy generator, outputs which are connected to the inputs of the correlator unit, the outputs of which are connected to the inputs of the decision unit, the signal input of the signal copy generator connected to the signal input of the correlator unit, t the act input of which, as well as the clock input of the decision block, is connected to the first output of the clock signal separation unit 2

The disadvantage of this device consists in a wide frequency band of low noise immunity due to the appearance of a flare error.

The aim of the invention is to reduce the bandwidth of the operating frequencies while improving noise immunity.

This goal is achieved in that a binary information transmitting and receiving device containing serially connected clock generator and signal generator on the transmitting side, the outputs of which are connected to the inputs of the signal selection unit, and on the receiving side, a driver of copies of the signals whose outputs are connected to the inputs of the block the correlator of the tori whose outputs are connected to the inputs of the decision block, the signal input of the signal copy generator connected to the signal input of the correlator block, clock the input of which, as well as the clock input of the decision block, is connected to the first output of the clock extraction unit; on the transmitting side, the binned information separation unit is inserted into dibits, the clock input of which is connected to the generator output of the clock signals, and the outputs to the control inputs of the selection unit signals, and on the receiving side, the first and second inputs, as well as the second output of the clock extraction unit, are connected respectively to the signal input, the signal output and the control input of the forcing counter of copies of the signals.

At the same time, signal signals are made in Eide for two signal generators, clock inputs of which are connected to the synchronizer output a and directly, via one delay line, are connected to the corresponding signal inputs of the switching unit whose outputs are the outputs of the signal conditioner whose input is the input of another line delays, the input and output of which are connected to the control inputs of the switching unit .. The driver of the signal copies is made in the form of two filters, the outputs of which are directly and through one delay lines are connected to one input of the switching unit whose outputs are the outputs of the signal copy generator, the signal input, the signal output and the control input of which are respectively the filter inputs, the output of one of the filters and the input of the other delay line, the input and output of which are connected with other inputs of the switching unit. The clock selection unit is made in the form of sequentially connected first (filter, second filter mixer, limiter, differentiator circuit and rectifier; the first and second inputs, the first and second outputs of the block are allocated to the clock signals, respectively, the input of the first filter and the second input the mixer, the outputs of the limiting bodies and the rectifier. In Fig. 1 shows a structural electrical circuit of the transmitting side, 4ig 2 - the same, the receiving side in Fig. 3 and 4 - voltage eshores, showing the work of the transmitting station The device contains on the transmitting side a shaper I signal generator 2 clock signals, a block 3 for selecting signals and a block 4 for dividing binary information into dibits, the shaper 1 of signals consisting of a synchronizer 5, a generator 6 and 7 of signals, lines 8-10 delay; ki and switching unit 1I, consisting of cells 12-15; block 3, the choice of signals consists of keys 16-19, and block 4 of dividing binary information into dibits consists of register 2: and decoder 21. On the receiving side, the device contains formavatal 22 : sopiy signals, block 23 correl tori, decisive block 24 and block 25 of the selection of clock signals 902 4 while the shaper 22 copies of the signals consists of filters 26 and 27, delay lines 28-30, and switching unit 31, consisting of cells 3235, the correlator block 23 consists from the correlators 36-39, and the clock extraction unit 25 consists of the first filter 40, the mixer 41, the second filter 42, the limiter 43, the differentiating circuit 44 and the rectifier 45. The device for transmitting and receiving binary information works as follows. On the transmitting side, a generator of 2 clock signals, acting on the control inputs of switching unit 11, connects to the output of cells 12 and 13 at odd clock intervals k. (k + l) To, where, 2,4, ..., signals from the outputs of the generators 6 7, arriving at their signal inputs, and the remaining intervals are signals from the outputs of the generator (ditch 6 and 7, arriving at their other signal inputs. In Fig. Pro, (Diagrams of changes in phases (1), 42 (t) of generators 6 and 7 over time are shown. At the output of cell 12, the signal phase changes, as shown in Fig. 3B, and at the output cells 13 in Fig. 3d At the moments of com-phase signals at the output, mutations ek 12 and 13 experience jumps multiples of 2g, which is equivalent to the formation of signals with a change in the if (t), - (j (t)) phases whose plots on the output of cells 12 and 13. Two periodically repetitive signals are formed with information phases V (t), YzCt), respectively. The remaining two signals are generated using cells 14 and 15. In Fig. 4a plots of the phases of the signals of the generators 6 and 7, as well as these phases, the signals passed through the delay lines 8 and 9, V {(t), VjCt) are shown. Signals from the generator output, 2 clock signals, delays kept on line 10, are connected to the output of cells 14 and 15 at clock intervals T) T de, 2.4, -, signals arriving at their signal inputs, and at other intervals time - signals to the other signal inputs of these cells. Then the phase of the signal at the output of cell 14 is changed as shown in FIG. 46, and at the exit of the cell 15 - in FIG. 4g. At the instants of phase switching, these signals experience jumps that are multiples of 27, which is equivalent to the formation of a signal with a phase varying at the output of cell 14, as shown in FIG. 4c, and at the exit of a cell 15 - on fkg. 4e. Thus, at the output of cells 14 and 15, two periodically repeating signals are generated with a triangular phase change Hjlt), 4 (t, respectively. If dibit 00 is transmitted to a clock interval of 2 Tr, then the same output appears at one output of the decoder 21 There is no signal at the outputs of the remaining elements. In this case, the key 16 is opened and the signal S, UU,), (t) with the information phase is sent to the communication line from the output of cell 12) Similarly, if dibit 01 is transmitted, then Another output of the decoder 21 appears to be the same signal for NOSTA bodies 2T, and the remaining elements at the outputs no signal, wherein the switch 17 is opened and the communication link from the output of cell 13 enters S, U) .U, cosKt f, Ci) with information jCt phase). In the same way, the keys 18 and 19 are opened in the transmission of the dibit Yu. Or 11. The signals S3 {t U co5 io -fcW3Ct);,. . . ) UoC03 u)) from the outputs of cells 14 or 15, respectively. At the receiving side, when incoming signals are received at the input of the driver of the 22 kope signal and the clock signal selection unit 25, the filters 26, 27 and 40 select discrete lines of the energy spectrum at frequencies f, f, f. At the end of the transients in these filters, at the outputs 2 of the filters 26 and 27, close to harmonic khpebans are formed, the phase of which changes, as shown in FIG. Behind. Simultaneous oscillations at the output of the filter 27 with a frequency fj are mixed in the mixer 41c by oscillations from the output (1miltra 40 with a frequency f. This signal goes to the control inputs of cells 32 and 33 directly, and to the control inputs of cells 34 and 35 via a delay line 30, while the outputs of the switching unit produce signals with a triangular phase change as well as at the output Ah of the 12, 13, 14 and 15 cells of the transmitter of the transmitting side signals. These signals are fed to the correlator inputs 36-39 of the correlator unit 23, the signal inputs of which receive the received signal and correlation processing occurs. the square wave, the passage through the differentiating circuit 44 and the rectifier 45, is converted into a pulse signal, with the intervals between the pulses being 2Td. From the output of rectifier 45, this signal passes to block 23 of correlators for interrogation of correlators and to decision block 24. If it arrives at the receiving side. signal S (t), then at the time of the survey of the correlators, the signal at the output of the correlator 36 is zero if there is no interference, and at the output of the other correlators 37, 38, 39 is zero, because the signals with a triangular phase change are orthogonal. At the time of the survey, decision unit 24 determines and compares the signal levels at the output of the correlators and decides whether the signal S (t) arrives at the input of the receiving side and, therefore, sends dibit 00. If the received signal is G2 (t), then at the time of the survey at the output of the correlator of the torus 37, the signal is different from zero, and at the output of the other correlators, it is equal to zero. The solver unit 24 then decides whether the input signal S2 (t) and, at c7, the transfer of dibit 01, is received. Similarly, when the signal G is received (t or S. respectively.

us.i 11649028 Techno-economic effect of the invention consists in narrowing the operating frequency band of the device for transmitting and receiving binary information 5 while improving noise immunity.

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Claims (4)

1. DEVICE FOR TRANSMISSION AND RECEIVING OF BINARY INFORMATION, containing on the transmitting side a series-connected clock generator and a signal shaper, the outputs of which are connected to the inputs of the signal selection block, 'and on the receiving side, a signal shaper, the outputs of which are connected to the inputs of the correlator block, the outputs which are connected to the inputs of the decisive unit, wherein, the signal input of the signal copy generator is connected to the signal input of the correlator block, whose clock input, as well as the clock input of the deciding unit are connected to the first output of the unit for clock signals, which is important because, in order to narrow the operating frequency band while increasing the noise immunity, a binary information separation unit is introduced on the transmitting side dibits, the clock input of which is connected to the output of the clock signal generator, and the outputs with the control inputs of the signal selection block, and on the receiving side, the first and second inputs, as well as the second output of the clock signal isolation block _χ signals are connected respectively to the signal the signal output and control input of the signal generator. 2. The device according to; p. ^ characterized in that the signal conditioner is made in the form of two signal generators whose clock inputs are connected to the output of the synchronizer, and the outputs directly and through one delay line are connected to the corresponding signal inputs of the switching unit, the outputs of which are the outputs of the signal conditioner, the input of which is the input of another delay line; the input and output of which are connected to the control inputs of the switching unit. 3. The device according to π. 1, characterized in that the signal shaper is made in the form of two filters, the outputs of which are connected directly and through the Delay lines 1164902 to one input of the switching unit, the outputs of which are the outputs of the signal shaper, the signal input, signal output and control input of which respectively, are the filter inputs, the output of one of the filters and the input of another delay line, the input and output of which are connected to other inputs of the switching unit. 4. The device according to π. 1, characterized in that the clock signal separation unit is made in the form of a first filter, mixer, second filter, limiter, differentiator circuit and rectifier connected in series, the first and second inputs, the first and second outputs of the clock signal separation unit being the input of the first filter and the second input of the mixer, the outputs of the limiter and rectifier.