SU1283992A1 - Device for clock synchronization of regenerator - Google Patents

Abstract

The invention relates to radio engineering. The purpose of the invention is to increase the synchronization noise immunity. The device contains reference gd 1, block 2 of the frequency difference compensation, block 3 of the phase-locked loop, set the 4 fronts, block 5 selection, asynchronous integrated receiver 6, block 7 switching, block 8 eliminating the edges of clock intervals with crushing , key 9, loss of signal synchronization generator 10, integrator II, control units 12 and 13 of the phasing speed and selection zone, predominance analyzer 14, allocation unit 15. skew signal, element 16, phase front analyzer (AFPF) 17, decoder 18 two b eye, front integrators (BIF). 19 and 20 and the zone enable signal generator (FSVZ) 21. The goal is achieved by introducing AFPP 17, decoder 18, BIF 19 and 20 and FSVZ 21, which reduces the delay time for switching on the action of the selection zone under conditions of intense distortion of the input signal. Given il. implementations of the decoder 18, BIF 19 and 20, FSVZ 21 and block 3 of the phase auto-tuning of the frequency. 3 il. i (L

Description

1

The invention relates to radio engineering and can be used in telegraph communication and data transmission for clock synchronization of regenerators.

The purpose of the invention is to improve the noise immunity of synchronization.

Figure 1 shows the structural electrical circuit of the regenerator clock synchronization device; Fig. 2 shows the structural electrical circuits of the decoder, the first and second blocks of the front integrators, and the signal generator h of switching on soHbij in Fig. 3 is the electrical block diagram of the phase locked loop.

The clock synchronization device of the regenerator contains a base generator 1, a compensation unit 2 of the NIN frequency difference, a phase locked loop 3, an edge selector 4, a selection unit 5, an asynchronous integrated receiver 6, a switching unit 7, a block 8 excluding the edges of clock intervals with crushing 9, loss of signal synchronization generator 10, integrator P, phasing rate control unit 12, selection zone control unit 13, predominance analyzer 14, i5 blocking section for skew signal, element OR I6, analyzer 17 of the phase position of the fronts, depthfrator 18, the first block 19 of the front integrators, the second block of the 20 front integrators, the driver 2 zone enable signal.

The decoder 18 contains a block of R6-triggers 22 and the block of elements And 23..

The first integrator block 19 of the fronts contains a block of AND-HE 24 elements, a block of meters 25, a block of 26 NO-elements, a block of 27 differentiating circuits, and a block of HE elements 28.

The second block of integrators 20 fronts contains a block of elements AND-NOT 29, a block of counters 30.

Shaper 21 of the zone enable signal contains a block of AND 31 elements, an OR 32 element, a NOT element 33.

The block 3 phase-locked loop frequency contains the correction block 34, the main frequency divider 35, block I5-triggers 36, block 37 to

five

five

0

five

0

five

A series of frequency dividers, a phase discriminator 38.

The device clock synchronization of the regenerator works as follows.

In the edge selector 4 (Fig. 1), the temporal position of the fronts of the input signal is sampled, for which a signal from the second output of the reference generator 1 is fed to the reference input of the edge fronts 4. Selected edges in synchronous mode through the switching unit 7 are fed to the input of the selection unit 5. In this mode, the selection unit 5 performs the selection of the fronts of the input signal according to the magnitude of the edge distortion, i.e. only the fronts that fall into the selection zone, which is fed to the input of the selection unit 5 from the output of the phase locked loop 3 (fig. 3), arrive for adjustment.

In synchronous mode, in block 3, phase-locked loop using speed control block 12, which is based on the RS-trigger, is activated by a variable integration capacitor 11 output signal, i.e. synchronization inertia increases, which contributes to its high noise immunity.

To eliminate the false imitation of the non-synpha state of the clock synchronization device of the regenerator, block 8 of the edge exclusion is used. With its help, in synchronous mode for analyzing the state of synchronism, only those edges of the input signal pass through the key 9, in the clock intervals of which there are no grinding pulses. This principle also makes it possible not to generate false signals of loss of synchronism when the clock synchronization device of the noise pulse regenerator is acting on the information input, which is especially important during changes of the working frequencies of the radio link.

In the common-mode search mode, the edges of the signal are fed to the adjustment and analysis of the state of the synchronization system from the output of the asynchronous integrated receiver 6, which performs the function of converting signal splittings to edge

distortion. At the output of the asynchronous integrated receiver 6, the temporal position of the edges of the transformed signal is discretized, for which a signal from the output of the reference oscillator 1 is fed to its reference input. The dedicated edges through the switching unit 7 are fed to the trim.

In order to eliminate spurious synchronization, when using a phase discriminator 38 with a symmetrical characteristic {in block 3, phase locked loop), switching unit 7 proceeds to unipolar synchronization. To this end, a clock signal from the second clock output of the phase locked loop 3 is supplied to the clock input of the switching unit 7.

In the synchronization search mode, the fronts from the output of the asynchronous integrated receiver 6 through the key 9 are fed to a variable capacitor 11, in which a small integration factor is included to shorten the synchronization search time. In parallel, the indicated fronts are fed to the signal inputs of the Fronts of the predominance analyzer 14, block 15, and the analyzer 17 of the phase position of the fronts (Fig. 2) for analyzing the synchronization state, the possibility of increasing the lag coefficient and switching on the action of the selection zone. The appearance of the signal from the output of the integrator, i. the inclusion of a large coefficient of integration of the clock synchronization device of the regenerator will occur if during the period of analysis no synchronization loss signal is generated.

The activation of the selection zone in the synchronous mode in the selection unit 5 is carried out using the zone control unit 13 (which is based on the RS flip-flop) under the influence of the signal from the output of the former 21, provided that the fronts of the input signal with a probability close to one, are within the selection zone. For this purpose, the latter is fed to the input of the Selection Zone ana5 5 and the inclusion of a small integration coefficient in the phase locked loop 3 and in the integrator I1. The mismatch criterion for the presence of symmetric signals in the signal (or

lizator 17 of the phase position of the front-55 absence) and asymmetrical transforms from the output of the phase matching block are based on the implementation of the 839924

the position and directs them to the first and second integrators 19 and 20, with the help of which the threshold value of the probability of finding fronts in the time interval of the selection zone is continuously determined. The principle of operation of the first and second integrators 19 and 20 is not limited to the framework of the established analysis cycle, but

fO is based on memorizing and accounting for the phase position of the fronts in the previous analysis cycle. In this case, the delay time for switching on the action of the selection zone in

5 conditions of intense distortion of the input signal and, thus, an increase in the noise immunity of synchronization is achieved.

If there is a constant in the signal

The 20 symmetric and asymmetrical dominances in the analyzer 14 are detected by allocating alternating fronts in special analysis zones and the value is fixed. If a

 the probability of this magnitude for the period of analysis is close to unity, then a “zon1” trip signal is generated, which through the OR I6 element and the zone control unit 13 enters the

30 input of the selection unit 5. As a result, the fronts of the input signal are passed to the trimming, to the mine, the selection zone. The high immunity of synchronization is achieved while maintaining a high inertia of the clock synchronization device of the regenerator. Thus, in the proposed regeneration clock synchronization device,

40 control of the selection zone and coefficient of inertia (phasing speed.

In the absence of synchronism in the imaging unit 10, a signal is generated,

45 under the influence of which, by means of the speed control unit 12 and the zone control unit 13, the action of the selection zone in the block is selected.

0 5 and the inclusion of a small integration coefficient in the phase locked loop 3 and in the integrator I1. The mismatch criterion in the presence of symmetric signals in the signal (or

5 absence) and asymmetric predominance is based on a pair of

Construction 3. Decoder 18 separates em, the fronts in accordance with their phase

fronts in the analysis zones, but in a different combination, respectively. The principle of the allocation unit 15 is based on this principle.

In addition, when synchronization is lost, the fronts through the switching unit 7 and the analysis through the key 9 begin to receive fronts from the output of the asynchronous integrated receiver 6.

Consider the operation of the clock synchronization device of the regenerator when the probability of finding the fronts of the input signal within

Breeding zones, composed Jup (eat P, 0.8.

 F

In this case, the signal for switching on the action of the selection zone appears at the output of the imaging unit 21 under the condition that the eight fronts of the input signal from ten incoming fronts are found in the time interval of the selection zone. Under this condition, the RS-flip-flop block 22 of the decoder 18 contains three RS.-flip-flops, the block of counters 30 of the block of integrators 20 contains three counters, with a capacity of eight edges each, and the block of counters 25 of the first block of integrators 19 also contains three counters, but their capacities equal to three.

When the power is turned on, the R5 triggers block 22 of the decoder 18 is set by the initial setup signal in the following way: the first trigger — to state 1, and the second — third triggers — to state O. The counters of the first and second integrator blocks 19 and 20 are zeroed. The phase position analyzer of the fronts 17 determines whether the incoming fronts of the input signal are located in the interval of the selection zone and outside of it.

With the help of the decoder 18, these fronts are guided by the oia of the monitors 25 and 30, respectively, through the blocks of the NAND elements 24 and 29 in accordance with their phase position.

Consider two examples of different phase positions of incoming fronts of the input signal.

Example I. In-phase state. The input signal is not distorted. The first eight fronts are in the time interval of the selection zone.

Since the first trigger of the RS-flip-flop block 22 of the decoder 18 is in state 1, these fronts arrive at the counting input of the first counter of the counter block 25 of the block

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integrators 19, which is completely filled with: k, using shaper 21, a signal is generated to activate the action of the selection zone.

, Example2. In-phase condition, input signal distorted. The 2nd, 4th, 6th, 13th, 15th and 17th fronts out of twenty who came did not fall within the interval of the selection zone. JO At this, the first front passes to the input of the first counter of the counter block block 25 of the integrator block 19, the second front sets the second trigger of the RS-flip-flop block 22 of the decoder 15 to the state 1 and simultaneously enters the input of the first counter of the counter block block 25 of the integrators 19. enters simultaneously to the inputs of the first and second counters of the counter 30 block, since the first and second triggers of the RS flip-flop block 22 of the decoder 18 are in state 1. The fourth front sets, the third

25 trigger blocks of RS flip-flops 22 decoder 18 in. State I and passes to the inputs of the first and second counters of the counter block 25 integrator block 19. Pu-front enters

30 at the same time to the inputs of the counters of the meter block 30.

Thus, the first counter of the block of counters 30 is filled with three pulses, the second - two, the third 35 one. The first counter of the counter block 25 is filled with two pulses, and the second one. The sixth coming front will be the third front that did not get into the zone. He simultaneously stumbles at the inputs of three counters of the block of meters 25. Since their capacities are three, a pulse is generated at the output of the first counter of the block of meters 25,

45 which zeroed it and the first counter of the counter block 30 at the same time. Fronts from the seventh to the twelfth inclusively fall within the interval of the selection zone and arrive simultaneously.

5Q, respectively, to the inputs of three counters of the block of counters 30. At the same time, the first counter of the counter of the block of counters 30 is filled with six pulses, and the second with the eighth (3rd, 5th, and 7-12th fronts).

 Since the capacity of the first, second and third counters of the block of counters 30 is equal to eight, then using the imaging unit 2I a signal is generated to activate the action of the selection zone

already after the passage of twelve edges of the input signal.

Claims (1)

Invention Formula A regenerator clock synchronization device containing a series-connected reference oscillator, a frequency difference compensating unit, a phase locked loop unit, a series-connected asynchronous integrated receiver, a key, an integrator and a prevalence analyzer, a series-connected deinterlacing signal generator, a loss of synchronism signal generator , the OR element, the control unit for the selection zone and the selection block, the front selector connected in series and the front exclusion block in clock intervals with fragmentation, sequentially connected phasing rate control unit and switching unit, information input and signal input whose FronFs are connected respectively to the outputs of the edge cutter and the asynchronous integrated receiver, the reference input of which is combined with the reference input of the edge fader and connected to the second output of the reference generator, the first and second clock outputs of the phase locked loop unit are connected respectively to the clock input of the divergence compensation unit frequency and combined clock inputs of the exclusion unit of the clock intervals with fragmentation and the switching unit, the output of which is connected to the input of the signal of the front of the selection unit, the input of the selection zone and the output of which are connected respectively to the output of the selection zone and the input of the signal of the front of the phase-locked loop, the output of the block of the edge of the clock intervals with crushing is connected to the first information input of the key, the control input of which is integrated with the control inputs of the integrated and installation are input torus and block phase autopod 283992. eight frequency and is connected to the output of the phasing rate control unit, the first input of which is unified with the control input of the loss of signal generator and connected to the integrator output, the second input of the phasing rate control unit is connected to the output of the loss signalformer fO synchronization, key output is connected to the signal inputs of the fronts of the block for skew signal and the predominance analyzer, the output of which is connected to the second input 15 elements OR, the combined information inputs of the edge cutter and the asynchronous integrated receiver are information input of the device, which is different from the fact that, in order to improve the noise immunity of synchronization, the front-connected phase analyzer, the first block of front integrators , the second block of front integrators and the zone turn-on signal shaper, while the signal input is the selection zone and the signal input of the front edges of the phase position analyzer, connected according 20 25 to the signal output The selection phase of the phase locked loop and the key output, the second output of the under-prevalence analyzer is connected to the control input of the dephasing signal extraction unit, the second output of the decoder is connected to the setup input of the second front integrator unit, the information input 40 of which is combined with the second information input the first block of front integrators, the code of the switch-on signal generator of the zone is connected to the second input of the control unit for the control of the selection zone, moves the first block decoder and fronts integrators, additional input of the second installation unit rbedineustroystva fronts integrators.