SU1442972A1 - Apparatus for tolerance control of time interval duration - Google Patents

Abstract

The invention relates to the field of measurement technology and is intended to control the duration of the time interval between two electrical pulses limiting this interval. The purpose of the invention is to increase the noise immunity of the device containing a pulse counter 6, the outputs of which are connected to the decoder 7, the one-shot 5 and D-trigger 4. The inverter 3 and blocks 9.1-9 are entered into the system. The control K, each of which contains a D-trigger 12, elements AND-NOT 13, 16 and counters 14 and 15 pulses. The device divides the controlled sequence of time intervals into a set of partial sequences, forms gates synchronized with partial sequence pulses, combines the gate using the latter when selecting the fronts of the original sequence. 1 hp f-ly, 6 ill. (C (L S

Description

four; four; e co

to

The invention relates to a measurement technique and can be used in systems for automated monitoring and processing.

The aim of the invention is to improve the immunity to interference.

The figure shows a functional diagram of the device with four control channels (p 4) 5 in FIG. 2 - 6 - time diagrams of its functioning.

The device contains a clock input 1, information input 2, inverter 3, D-flip-flop 4, one-shot 5, counter 6 pulses, the decoder 7,

the element AND-NO 8, blocks 9.1 - 9.p control, the element AND-NOT 10 and vyhohodu about the bus P.

Information input 2 of the device is connected to the D-input of the trigger 4, Clock input D of the trigger is connected to the input of the inverter 3 and connected to the clock input 1 of the device. Inverted output

torus 3 is connected to the third inputs of blocks 9.1 - 9.P control. The counting input of the counter 6 pulses is connected to the clock input of the decoder 7 and the first input of the NAND element 8 and through the one-vibrator 5 is connected to the direct output of the D-flip-flop 4 pth connected to the second inputs of blocks 9.1-9. The first inputs of blocks 9.1-9.p control are connected by a bus of logic units, and the outputs are connected to the inputs of the NAND element 10 connected by the output to the second input of the NAND element 8, the output of which is the output bus I1 of the device.

Each n, th block of control contains a D-flip-flop 12, the first element IS-NOT 13, the first 14 and second 15 pulse counters and the second element 16.

The first input of the control unit is connected to the information input of the D-trigger.

Section 12, the inverse output of which is connected to the nepBONry input of the element AND-HE 3, the second input of which is connected to the inverse input of the D-trigger setup 12 to the zero state and connected to the second input of the control unit, and the output of the I-HR 13 is connected to the combined the installation inputs to the zero state of serially connected first 14 and sec-1

five

0

0

five

0

0

15 counters, the counting input of the first of which is connected to the third input of the control unit, and the information outputs of the second 15 counter are connected to the inputs of the I-HE element 16, the output of which is connected to the clock C-input of the D-trigger 12 and is connected to the output of the control unit.

The device works as follows.

The information input 2 of the device receives the sequences of rectangular pulses under study (Fig. 2.a), and the clock input 1 receives the clock pulses (Fig. 2.b), the D-flip-flop 4 binds the information signal to the positive edges of the clock sequence. The plot of the output signal of this trigger is shown in Fig, 2,3,

The single-shot 5 is triggered by the output signal drops from the D-flip-flop 4 and generates short single pulses (Fig. 2d). At the outputs of the decoder 7, zero-level pulses are formed, equal to the duration of the clock pulses and synchronized with the positive differences of the signal of the direct output of the D-flip-flop 4 (fig. 2.e, f, g, g).

Blocks 9 controls work identically, but with a shift in time by the amount of the monitored time interval,

In the initial state, the D-flip-flops 12 are set to one state, in which the potential: the inverse trigger output through the AND-NE element i3 keeps the counters 14 and 15 of the pulses in the zero state.

Upon receipt of negative pulses from the output of the decoder 7 to the second input of the control unit (Fig. 2.d., 5 or on an enlarged scale of Fig. 1), D-flip-flop 12 switches to the zero state (Fig.3 and) and after the end of the pulse At the output of the decoder 7, the R inputs of the counters 14 and 15 form zero voltage levels (FIG. K), which enable the counters.

The inverted clock sequence, which applies to the counting input of the counter 14, triggers the operation of both counters 14 and 15. The time dependence of the total content N (t,) of the counters is shown in FIG. 3, l, after time

five

0

I.I - M.A.I), in a predetermined manner, synronized with the information signal, and at the output of the first element AND-HE 8, the release potential (Fig.Z.N.).

If the duration of the interval is time L, the limited pulse

(Fig: 5),

4t

i t

meets the norm i

and the duration of in

L1.

2

(FIG. 3) since the start of counting, a zero potential is formed at the output of the AND-HF element: 16 (FIG. 3.).

When the counters 14 and 15 g overflow, the contents of N (t) of the counters zero, a positive voltage drop is generated using the AND-NOT 16 element, through which a logical unit is written to the D-flip-flop 12. At the inverting output of the D-flip-flop 12, a logic zero level is set, which locks the counters 14 and 15 in the zero state through the NAND 13 element. Thus, for each output impulse - 15 sus of the decoder 7, arriving at the second input of the corresponding control unit 9., A negative impulse of the temporary gate with a duration g is produced (FIG. 3.), the onset of which is 20 ° which is the duration of one of the delayed relative to the pulse controllable, x time intervals

cooTBeTCTBveT

The interval between other pairs of impulses exceeds the value, / fp, TO only this impulse enters the time gate formed by the third control unit and passes through the first AND – NE 8 element to the bus 11 of the device (F1-1g.5, o), signaling

decoder 7 at time 1), and I N, (Ni - l) / f o and 4- N, / f

about and

specified rate, taking into account the established floor tolerance. If during the time interval

about and

where fo is the clock frequency; N, N - capacities, respectively, of the counters 14 and 15, the Duration of the 4G interval is equal to the width of the tolerance field, and the value 1) + u l / 2 is the specified setting relative to which the monitoring is performed,

The output pulses of the IS-NE 16.1 - 16.4 elements of the four control units (Fig.4, m, 1 - M.4) are combined by the IS-NE 10. element (Fig.4.n,) and arrive as a selection signal to the second input of the element AND NOT 8,

FIG. 4.G.1 and FIG. 5, D.2 shows the time distribution of the positive fronts of the pulses formed by the single vibrator 5.

The admission control of the time interval is carried out as follows.

The case of the formation of a single vibrator 5 from a sequence of input pulses of a pulse sequence is shown in Figure 5.g.2.

In case 4, the first control unit operates on the 1st, 5th, 9th, 13th and m, d, output pulses of the single-oscillator, and the second, third and fourth control units - on the 2nd, 6th, respectively. th, 10th, 14th, ..; 3rd, 7th, 11th, 15.-MU,.,; 4th, 8th, 12th, 16th, .. and t, d, impulses.

Each one-shot launch leads to the formation of one of the blocks controlling the temporary gate (figure 5.m.

I.I - M.A.I), in a specified manner synchronized with the information signal, and the appearance at the output of the first element AND-HE 8 of the unlocking potential (fig.Z. N.).

If the duration of the time interval is L, the limited pulse

(Fig: 5),

4t

i t

meets the norm i

and the duration of in

L1.

2

° that the duration of one of the controlled, x time intervals

° that the duration of one of the controlled, x time intervals

between intervals of other pairs of impulses exceeds the value of / fp, TO only this impulse enters the temporary gate formed by the third control unit and passes through the first AND-NE 8 element to the bus 11 of the device (F1-1g.5, o), signaling

5 g, w - 15 o-20 ° that the duration of one of the controlled, x time intervals

cooTBeTCTBveT

 ,

thirty

35

specified rate, taking into account the established floor tolerance. If during the time interval

A 25LB pulsed single-shot 5 (FIG. 6, g, 3), a pulsed disturbance appears at the input of the device, to which the single-shot reacts by forming, for example, 2nd, 3rd and 4th and myles {FIG. bg), then the first, second and third blocks of control are triggered by the same one-shot input pulses as before (FIG. 3), and the fourth by 4th, 8-Nry, 12th, 16th, etc. impulses. As before, after each output pulse of the one-shot 5, a temporary gate formed (FIG. 6 m .1.2 - m. 3.2), and at the output of the second element AND-NE 10 a selection signal appears (FIG. 6, n .2). However, only the impulse passes to the device bus 11 (FIG. 6.0.1), which corresponds to the 1Ch standard, taking into account the width of the tolerance field.

Thus, the invention allows to increase the noise immunity when exposed to no more than n-1 impulsive noise during controlled

5Q time interval.

Improving the noise immunity is achieved by dividing the controlled sequence of time intervals into n partial sequences, forming a temporary gate synchronized with the pulses of partial sequences, combining the temporary gate and using. using them when selecting fronts

40

45

the initial sequence

1442972

with

in n and el

Claims (2)

Invention Formula 1 A device for tolerance control of the time interval duration, containing a decoder, a single vibrator, a trigger, a counter, the counter outputs are connected to the inputs of the decoder, the clock input of which is connected to the output of the one-vibrator, in order to increase the noise immunity, it additionally introduces two IS-NOT elements, an inverter and n control units, with the D-trigger information input connected to the input information 1st to 5th are connected to the second inputs of the control units, respectively, from 1st to 5th, the third inputs of which are combined and connected to the output of the inverter, and the outputs of all control units are connected to the n inputs of the second NAND, 2. The device according to claim 1, 1 and 2, is that the control unit contains a D-flip-flop, the first and second elements are NAND, the first and second counters, the first input of the control unit is connected to the information D-BXO-house D-flip-flop, the inverse output of which is connected to the first input of the first NAND element, the second input of which is connected to the inverse input of the D-flip-flop setting to zero state device bus, input bus 20 is connected to clock pulses of which are connected to the combined input of the inverter and clock input of the D-flip-flop, the direct output of which is connected via one-shot to the counting input of the pulse counter and the first input of the first NAND element whose output is the output of the device and the second input is connected to the output of element NAND, the first inputs of the n control units are combined and connected to the bus of a logical unit, and the outputs of the decoder Fy second first element block input I-NOT is connected to the combined inputs of the installation of the first and second counters connected in series to the zero state, the counting input of the first of which is connected to the third input of the control unit, and the information outputs of the second counter connected to the inputs of the second element AND-NOT whose output is connected to the clock With the D-trigger input and connected to the output of the control unit. H.1 eleven AG.2LT .5 m and; n M.f.1 n.i.i M. 1 ML.1 H.I Phage. 1Л1 and: P P P Pu, z.5 Fi.g.6