SU1417005A1 - Control apparatus - Google Patents

Abstract

The invention relates to the field of computer technology and can be used in the construction of control devices for universal computers and microprocessors. The aim of the invention is to reduce the capacity of the memory block by allowing the organization of subroutines nested in each other. The device contains an address register, a memory block, a command register, a group of counters, a generator of control signals, a program level counter, a decoder, a multiplexer. The introduction of a multiplexer, a program level counter, a decoder and a group of counters ensures the achievement of a goal. 4 il.

Description

1i /

The invention relates to computing and may find examples. no-those when building control devices for universal digital computers and microprocessors.

The aim of the invention is to reduce the capacity of the memory block by allowing the organization of subroutines nested in each other.

FIG. 1 shows a functional diagram of the proposed device; FIGS. 2 and 3 are variants of the circuit implementation of the control signal generator; Fig. 4 shows the graph of the device operation.

The device (Fig. 1) contains the address register 1, memory block 2, command register 3, zero counter 4, control signal generator 5, program level counter 6, first output 7 microoperations of the control signal generator, counter group 8, multiplexer 9 , the decoder 10. In addition, in FIG. 1, the positions of the seventh 11, eighth 12, first 13, second H, third 15, fourth 16 ;, fifth 17 and sixth 18 bits of the second field of microoperations, input 19 of the logical conditions of the device.

The control signal generator 5 (the first version) contains (FIG. 2) a decoder 20 having three groups of inputs, a clock signal generator 21, a ring counter 22 and a set of logic circuits 23 whose outputs form the first and second groups of outputs of the generator 5 control signals. The ring counter reset input is the generator 5 reset input control input; their signals,

The control signal generator 5 (second variant) contains (see, FIG. 3, the microprogram control unit 24 having three groups of inputs 25, a fixed memory block 26, the first 27 and the second 28 groups of outputs of which form the corresponding groups of outputs of the signal control generator 5 and a clock signal generator 29. In this case, the reset input 30 of the control signal generator 5 is connected to the setup input of the initial state of the microprogram control unit 24. The latter can be implemented on the K589IK01 microcircuit and the permanent memory block 26 oshema series

0

five

0

five

0052

K556. In the graph diagram (FIG. 4), microoperations are labeled with positions 31-43,

All units of the proposed device are standard and easily implemented on integrated circuits, for example, the K155 series,

The device provides control of the computational process in accordance with a multi-level program located in memory block 2. This program contains sequences of commands at various levels. Each command of a higher level in the process of execution is replaced by a sequence of commands (t, e. By the program) of a lower level and t, e. Finally, a first-level command is represented by a sequence of traditional machine (zero) level commands; the addresses of which are given by counter 4, Commands from level 1 to level 5 also contain an operation code and an address part. The operation code field indicates one of four possible command types: IMP unconditional jump command; conditional transition command ICW; OPC operations team; end-of-life command. The address field indicates the transition address for the transition commands or the start address of the command execution program at the next lower level for the operational commands, s.

The device works In accordance with the graph-scheme (Fig, 4),

After the signal has been sent. The reset, which comes to the input of setting the initial state of the device, sets the level counter of program 6 to the state n, the nth counter 8 to the zero state. In addition, the initial state of the control signal generator 5 is established. After the signal is removed, the generator 5 control - ush} 1x signals in bit 14 of the second group of outputs generates a pulse. Thanks to this, micro-operation 31 will be executed - Send the contents of i-ro counter 8 to address register 1. "Each micro-graph-circuit (FIG , 4) for greater consistency, is marked with the numbers of the corresponding bits of the second group of outputs of the generator 5 of the control signals. The micro operation 31 is provided by

that the outputs of one of the counters 8 through the multiplexer 9 are connected to the inputs of the second group of information inputs of the register 1 address 0

five

0

five

314

Ca, the i value of counter 8 is determined by the state of the program level counter I. And at the initial moment, the initial state of the nth counter 8 will be written to the address register 1. Then the control signal generator passes the next step: 32 - Read the code from memory block 2 in register 3 commands. In this case, pulses are generated at 15 and 16 bits of the generator 5 of control signals. The first is fed to the input of the block 2 memory, and the second to the input of the resolution of the register of 3 commands. This provides a sample of the command code from memory block 2 and writing it to the command register 3. During the first pass after a reset, the first n-th level command will be recorded in the command register. Then, micro-operation 33 - Increment i-th counter 8 is performed. This action is provided by a pulse in discharge 11 of the second group of outputs of the control signal generator 5, which is fed to the increment inputs of all counters 8 and counter 4 of commands. However, the decoder 10 provides a sample one counter, the number of which corresponds to the current state of the program level counter 6 (counter 4 is selected when the program level counter 6 is zero). On the first pass after a reset, the nth counter 8 is selected, so that only it will be incremented. Further operations depend on the type of command. First, a test is performed 34 - IMP command. This check is implemented by the logic of the generator 5 of control signals by comparing the operation code of the command received from the second group of outputs of the register 3 of the commands to the second group of inputs of the generator 5 of the control signals with the known command code IMP. If the comparison gives a positive result, then micro-operation 35 - Enter into the i-th counter 8 is the address from the register of 3 commands. To perform this action, the control signal generator 5 generates a pulse in bit 12 of the second group of outputs, which is accessible to the recording resolution inputs of all counters B and counter 4. However, due to the action of the sampling inputs controlled from the outputs of the decoder 10, the recording will be implemented only in

counter 8 corresponding to the current level. With these actions, the transition address from the address part of the command through the first group of outputs of the register of 3 commands will be transferred to the counter 8 of the current level, which ensures the unconditional transition prescribed by the command. After this, the generator 5 of control signals provides for the repetition of micro-operations, starting with block 31. If the operation code does not match the code of the IMP command, then test 36 is performed - ICN command.

It is performed in the same way as micro-operation 34. If the test result is positive, then test condition 37 - is performed. This check is also implemented by the generator logic.

5 control signals by comparing a predetermined condition code CN with a true value received at the inputs 19 of the condition signals. If the result of the comparison is positive, then

The transition is completed (micro-operation 35 is implemented), otherwise, micro-operations are repeated, starting from block 31 (i.e., sampling of the next command).

If the operation code is not the same as the ICN command code, then micro-operation 37 - OPC command is executed. This micro-operation is carried out similarly to 34 and 36. If the command is indeed operational, then the generator 5 control signals executes the micro-operation 39 -. This microoperation is fulfilled by the logic of the control signal generator 5 by comparing

the code of the current level coming from the outputs of the counter 6 of the program level to the inputs of the second group of inputs of the operation code of the generator 5 control signals with a zero code. If the result

the comparison is negative, i.e. the program level is not zero, a decrease in the program level is realized. This is provided by micro-operation 40 - Decrement a 6-level counter.

programs. At the same time, the generator 5 of the control signals generates a pulse in the line 17 of the second group of outputs, which is input to the decrementing and counter 6 of the program level. By

55

This is barely accomplished by the described micro op 35, thanks to which the address part of the operational command is entered into the program counter of the subordinate level, which prepares

the next control cycle If the result of the comparison is positive, i.e. , and the next command is addressed by the counter A of the commands, then it is to be executed. This is provided by block 41 - Execute a command. Here, the generator 5 of the control of the nuix signals generates a pulse in section 13 of the second group of outputs, which ensures the recording of the address from the address part of the register of 3 commands via the first group of outputs to the address register through the first group of inputs.

At the end of this sequence, the program returns to the 1st program level, the next command of which causes the next successively. A number of zero level commands, etc. until a level 1 END command is found. Going on here

appeal to level 2, etc. The process continues until the entire n-th level command sequence is completely executed.

Thus, the proposed device provides control computing

This prepares a sampling of the blinding process in accordance with

ka 2 memory operand addressed by the command. In addition, the control signal generator 5 on the first group of outputs generates a series of control pulses fed to the operating device through the control signal output lines of the device. All this ensures the execution of the zero-level command. Then the next control cycle resumes. If checks 34, 36 and 38 gave a negative result, then the command END is recorded in register 3 of the commands. Then check 42 - 1 n is performed. If the result is negative, then this means that the sequence of commands i -ro level and it is necessary to move to a higher program level. In this case, microinstruction 43 is executed - Increment the program level counter 6. The control signal generator 5 in this case generates a pulse in bit 18, which is fed to the increment input of program level counter 6 and increases its contents by one, ensuring the device moves to a higher level. If test 42 gives a positive result, it means that the program of the highest level n is completed. In this case, the generator 5 control signals block all output pulses and the device goes into Stop state. Consider the cyclic graph-diagram of the device (FIG. 4) 5 it is easy to make sure that the program started from level n sequentially lowers its gg multiplexer, and the input is the initial

level until it reaches the level O, where a sequence of commands will begin to be executed, ensuring the completion of one command of the 1st level.

Claims (1)

The device installation is connected to the installation input of the O p-th counter and to the installation input of 1 program-level counter, the output of which is connected by a Level Program. Invention Formula A control unit containing an address register, a memory unit, a command register, a control signal generator, the outputs of the command register address field are connected to the first group of information inputs of the address register, the output of which is connected to the address input of the memory block whose output is connected to the information input command register, exit code floor operation of which is connected to the first input of the operation code of the generator of control signals, the input of the logic conditions of the device is connected to the input of the logical conditions of the generator of control signals, the output of the first field of microoperations of which is the output of device microoperations, the outputs of the first to fourth guides The signals are connected respectively to the first and second synchronization inputs of the address register, to the memory block expansion input, to the command register synchronization input, the initial setup of the device is connected to the reset input of the control signal generator, characterized in that, in order to reduce the memory block capacity by providing the possibility of organizing n nested one to another subprograms, it additionally contains n + 1 counters, where n is the number of nested subprograms, a program level counter, a decoder. device installation is connected to the input. installation house in the Oh p-th counter and with the installation input in 1 program level counter, the output of which is connection7i41 a ken with the input of the decoder, with the control input of the multiplexer and with the second input of the operation code of the generator of control signals: the first through (n + 1) -th decryptor signals are connected to the permission inputs from the first through (n + 1) th counters, information outputs of which are connected respectively to the first through (n + 1) -th information inputs of the multiplexer, the output group of which is connected to the second group of information inputs of the address register, the fifth and tes70058 The outputs of the second FIELD of microoperations of the control signal generator are connected respectively to the inputs of the subtraction and addition of a program level counter unit, the seventh output of the second field of the micro operations of the control signal generator is connected to the inputs of the addition of a unit, from the first to (n + 1) -th counters, the eighth output The second floor of micro-operations of the control signal generator is connected to the synchronization inputs from the first to (n + 1) -th counters. figure 1 R 23 & 21 RCl R n 2 0 FIG. 2 Fig.Z