SU1467556A1 - Channel simulator - Google Patents

Abstract

The invention relates to computing technology and can be used to monitor and diagnose peripheral devices having an output on a 2K system interface (for a CM-2, CM-2M computer), during maintenance and repair. The aim of the invention is to reduce the hardware costs of the simulator. The goal is achieved by the fact that the simulator containing a RAM block, a command type decoder, a sampling signal switch, an input block, reception and output registers, a permanent memory block, fixed and RAM memory address counters, an increment counter, a register memory addresses, mode register and clock generator, interface signal register, readiness register and comparison circuit are entered. 7 il. with (L

Description

one

The invention relates to computer technology and can be used for maintenance and repair of digital equipment and computer peripheral devices having an output on a 2K system interface (for computers of type CM-2, CM-2M).

The aim of the invention is to reduce the hardware costs of the simulator.

FIG. a block diagram of a channel simulator is presented; FIGS. 2-7 are a functional diagram of a control unit, a constant memory address counter, an increment counter, a clock generator, a sampling signal switch, and an input unit.

The simulator contains (Fig. 1) block 1.input, block 2 of RAM

(RAM), a command type decoder 3, a sampling signal switch 4, an exchange register block 5 and control devices 6. Unit 5 of the exchange registers consists of a register 7 for receiving information, a register 8 for information and a register 9 for interface signals. The control device 6 comprises (FIG. 2) a permanent memory address counter 10, a comparison circuit 11, an increment counter 12, a counter

13 addresses of RAM, register

14 addresses of RAM, block

15 permanent memory (PIZU), 16 clock generator, register 17 modes

and readiness register 18.

To implement the exchange on the 2K system interface in the simulator pre4

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outputs for sampling buses 19 (WED-K, FBG1-K), information receiving buses 20 (0-T tires - 15-T), information buses 21 (information buses 0-К - 15-K buses 22 interface signals (VP -K, OST-Kp PSB-K, VD-K, PR-K, OSB-K), readiness buses 23 (TRP-T, GT1-T). The program data (commands operands, constants) are recorded in block 2 (having arranging 64x16 bits), starting with a cell addressed by the counter 13 Setting the address of the RAM to the counter 13 is performed from block 1,

Block 3 decrypts the word set at the output of block 2 based on the type of command (I / O or address), controls the recording of instruction instruction code bits in counter 10, and enables operation of switch 4 on the basis of I / O command.

Information from the external device is received via the 0-T-15-T buses and stored in register 7, the contents of the cell block 2 are output to the external device via the 0-K-15-K buses through register 8, and the formation of control potentials .- on tires 22 (VP-K-, OST-K, PSB-K, VD-K, PR-K, OSB-K) register 9,

The device 6 provides the simulator operation according to the principle of firmware control, organizes the input-output procedure and the logical processing of the input information according to the program, based on the received list of input-output commands commands (with and without the VP-K signal) and the address commands required and sufficient for compiling a program that allows a full-fledged check of the external device via the 2K system interface

Counter 10 sets the address of the word PROM with the required set of microinstructions.

The counter 12 generates a signal for incrementing the counter 10 according to the overflow condition M n-1, where M is the content of the word block 2.

The counter 13 determines the addresses of the RAM layer on which the information is input or output.

Register 14 provides the storage of the address of the RAM of the program's address command.

Block 15 provides storage of microinstructions and conditions for commands with analysis of conditions.

The generator 16 generates a sequence of six clock cycles necessary for the temporary assignment of all the microoperations of the device.

Register 17 modes of operation sets one of three modes of operation of the device: automatic, semi-automatic or manual.

The readiness register 18 records the presence of effective potentials on 5 readiness tires 23 of the TRP-T, GP-T and, if available, enables the increment of the counter 10.

Counter 10 of the address of the permanent memory contains () elements AND-OR- 0 NOT 24-28, elements NOT 29-33, element AND-NOT 34, element NOT 35, elements Y-NOT 36-39, counters 40 and 41, and element 42.

The increment counter 12 maintains (5) an element NOT 43, counters 44-47, AND-NOT 48 and 49 elements.

The 16 clock generator contains (FIG. 5) a master oscillator 50 consisting of elements HE 51, resistors 52, a quartz resonator 53 and a capacitor 54, counters 55 and 56, AND-NOT 57 elements, triggers 58 and 59, AND-NOT elements 60-64, decoder 65, capacitor 66, elements HE 67 and 68, control input 69, start input 70 and resolution input 71.

The switch 4 of the signal sample contains (6) the element NOT 72, the trigger 73. and the elements And 74 and 75.

Input block 1 contains (FIG. 7) counter 76, decoder 77, elements OR NOT 78-82, elements NO 83-86, AND-HE elements 87 and 88, comparison element 89, trigger 90, AND-NE element 91, the element OR NOT 92, the element NOT 93, the element AND-NOT 94, the trigger 95, the element OR-NOT 96, the elements AND-NOT 97 and 98, the trigger 99, the element AND-NOT 100, counter 101, the element OR-NOT 102 , decoder 103, buffer register on triggers 104-119, keyboard buttons 120, diodes 121, and capacitors 122. FIG. 1-7 also shows connections 123-131 between simulator blocks.

The channel simulator works as follows:

In block 2, using the data keyboard of block 1 with address control from the counter 13, the command is entered

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50

514

(from the received command list) and program data. The interface unit of the external device being monitored is connected to the terminals 19-23 of the device.

When you press the Start button on the keyboard of the control unit t, the generator 16 is turned on, providing, starting from the fifth cycle, a temporary sequence of measures and performing nporpat-iMbi, starting with the command addressed by the counter 13.

Block 3 analyzes the 16-bit RAM word (O is the highest, 15 is the least significant word bit) for a command type indication of bits 0-5 and allows writing bits 0–4 of block 2 (in the case of address commands) or bits 5– 9 (in the case of I / O commands) to the five most significant bits of the seven-bit counter 10 (the two low-order bits of the counter 10 are zeroed in this operation). Writing the specified bits into the counter 10 installs the block 15 at the address starting with which, in the volume of four neighboring cells of the EPROM, the set and sequence of microinstructions for the command chosen from the RAM are stored

Addressing within the area of storage of micro-commands of the software command. The drives are performed by two lower bits of counter 10.

The presence of a logical 1 at the output of block 15 in bits 0-16 of a twenty-four-bit word means the presence of a corresponding micro-command, each of which performs a specific operation in the simulator.

The presence of 1 in bits 21-23 of the micro-instructions connected to the input of counter 10 means the permission to analyze the program branch conditions when executing certain commands. When these conditions are met, the first clock counter 10 increments and, therefore, leaves the address of the PROM word, where microcommands are stored in case this condition is not met. In the SFC and .. SFS commands, the availability of the ready signal (GT-0 or GT-1) from readiness register 18, In the CPB command, a sign of the equality of the word RAM with the contents of register 7 from the comparison circuit 11 is analyzed. In command I SZ, the sign of overflow of the counter 12 is analyzed.

Incrementing counter 10 when

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named us- in the presence of

generator 16.

0

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The execution of one of the rules is performed by the input of a clock from the output

For the rest of the commands in the received list, bits 21-23 are not programmed.

Commands are executed in cycles, the cycle of operation of the device is equal to six 4 M, the sequence of which is generated from the output of the six-bit decoder 65.

The execution of a program instruction lasts no more than four cycles, therefore the oldest five bits of the counter 10 do not change at the time of its execution, and the change of sets of microcommands from cycle to cycle is achieved by enumerating its two lower bits. In steps 2-5, micro-operations are performed, provided by the program command, in the sixth cycle, the counter 10 is incremented by input (in the first cycle, it can increment additionally only in commands with a condition), goes to the next address, etc. The sequence of procedures within the cycle is determined by the cycle number.

In the last (of 4) machine cycle, at the output of the twentieth bit of block 15, 1 is set, arriving at the input of counter 10 and providing the new address in the sixth cycle, resulting in the execution of the next program command.

Switch 4 (Fig. 6) provides control potentials for one of the WROB-K, VBR1-K pins (to select the appropriate interface module card of the plug-in peripheral device) based on the I / O command sign at the time of its execution . If bit 15 of block 2 contains 0, then the control potential will be on the wedge-k bus, if 1 - then on the fdr-k bus.

Block 5 receives a sixteen-bit word from the 0-T-15-T bus from an external device when executing the LIB command (for a zero-bit micro-command of block 15) in the receive register 7, issuing a sixteen-bit word from the 0-K-15K bus RAM through the issuance register 8 on the PTA command (a microcommand of the first digit of block 15 is set), forms

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1467556

interface signals VP-K, OST-K, PSB-K, VD-K, PR-K, OSB-K six-bit register 9 (by microcommands of the second and seventh bits of block 15) when executing input-output commands. The time linking of the generation of interface signals by the register 9, the reception and output of information by the registers 8 and 7 is carried out by the generator 16. The recording in block 2 is also synchronized by the generator 16.

At the STB command, the contents of register 7 are entered into the cell addressed by the counter 13 by the microinstruction from the eighth bit of the block 15,

Scheme 11 Comparison works always, unlike counter 12, which increments the cell contents of block 2 by the ninth microcommand bit (when executing an ISZ command). The modified cell contents of block 2, in the presence of the tenth digit of the microcommand, are entered into block 2 at the same address at which reading occurred when the command was executed. Writing to the pesticide counter 13 is carried out when executing address commands. Counter 13 in the procedures for executing these commands takes the values of the addresses of addresses or calls contained in the six least significant bits of the RAM word executed by KOMaiJ in the presence of a microcoma.

To store the address of the word RAM of the command being executed, a register 14 is used, which is written to the output of the counter 13 at the moment of accessing block 2 for the next program command. Recording is carried out with the appearance of a logical 1 from the output of the twelfth bit of block 15

After the calls to the cells of the RAM in the process of performing the address instructions, the address of the command being executed is rewritten from register 14 to counter 13 under the control of the thirteenth bit of the microcommand.

If there is a logical 1 in the fourteenth microdirectory of the microcommand in the fourth cycle, the counter 13 is incremented, thanks to which the output to the address of the next program command is provided.

The register of 17 operating modes is three-bit, shift, switched on in a ring circuit. An alternate installation 1 at its outputs is carried out

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with each pressing of the corresponding keypad button of the control unit 1, the initial state of the register — the presence of 1 in the first digit — corresponds to the automatic execution of the program, in which the generator 16 can be stopped only when the program comes to a stop command. A sign of stopping the generator 16 in the fifth cycle in this case is the appearance of a logical 1 from the fifteenth bit of the microcommand.

The presence of 1 in the second bit of register 17 corresponds to a semi-automatic mode of operation, which is in tone, that the stopping of generator 16 in the fifth cycle occurs after the completion of the next program command (if there is a logical 1 from the output of the twentieth micro-command)

The presence of 1 in the third category of the register 17 corresponds to the manual 5 mode of operation of the simulator. The generator 16 is stopped in each cycle cycle.

In any case, the continued operation of the device in the selected mode can be continued by pressing the start button, the signal from which is fed to the start input of the generator 16.

The two-bit readiness register 18 records the GT-0, GT-1 tires from an external device for subsequent program analysis (when executing SFC, SFS commands), and when the 15th digit is zero, these commands are recorded tires GT-0 in the first, bit, and with a single value - in the second. Record made 0

five

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It appears at the appearance of a logical 1 in the sixteenth bit micro command.

The zero content of the RAM cell when accessed by the counter 13 for the command corresponds to an empty NOP command, which can be used as a time delay in the program. If the program does not use the entire amount of RAM and does not contain any program shutdown commands or there are no wait and return cycles in the program, then at the end of the program, the counter 13 sequentially increments in every fourth clock cycle (if there is a logical 1 in the fourteenth category of microcommand), after state 77 (in the eight-dimensional code) o6Hv0

and, starting at address 0, the program is executed again.

From the decoder 3, via communication 123, the PR.ADR or PR.V-B signals are sent to the input of the counter 10. The first of them (ADR), indicating the reading of the address command from the RAM, commutes bits 0-4 of the command format to the information inputs of counters 40 and 41, and the second (PR.V-2), using the same follow path - dy 5-9 format I / O commands. These bits, which determine the address of block 15, beginning with which the command execution firmware is stored, are recorded by the AND-NE element 34 by a low level signal that appears in the sixth cycle when there is a logical 1 from the 20th bit of block 15 (P2 2d), responsible for starting the execution of the next program command.

The search of the EPROM cells within the firmware of the executed command is performed by incrementing the counters 40 and 41 on the leading edge of the signal from the output of the I-HE element 42. The counters are incremented in the sixth cycle (natural increment) in the absence of 1 at the output of the 20th bit of block 15 (i.e., after parallel writing to the counters and at the first cycle (conditional increment) in commands with condition analysis; for SFS and SFC readiness sign from register 18, for CPV sign of equality from comparison circuit 11, and for ISZ - overflow sign with counter 12. Signs are masked by the corresponding bits of 21-23 micro-instructions.

Writing counters 44-47 of the 16-bit RAM word is performed by setting a logical 1 at the output of the 10th bit of block 15 (which is set when executing the microprogram for executing an ISZ command), and the increment is by setting 1 from the output of bit 9 of block 15 In this case, the trigger detects an overflow (the transfer signal from counter 47), on the IS-NOT elements 48 and 49 for the execution time of the microprogram the command is unlocked. The HE element 43 is required to create the effective value from the 10th bit of block 15 (Fig. 4).

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The generator 16 (figure 5) provides for the generation of clock sequences in one of three modes,

my register 17.

Trigger 58 causes reset of counter 55 (i.e., generator stop) in the following cases.

If register 17 is in the state command. In this case, in step T6, when the current command completes (on sign 20), a logical O appears from the output of the K-NE 63 element, causing the reset of the flip-flop 58 via the AND-HES 64 element.

Similarly, in the state of Tact, the trigger 58 is reset after generating the next clock cycle from the NAND element 61.

0 With the help of the IS-NOT element 62, the stop in the step T5 is reached by the command HLT (when it is executed, a logical 1 is set for bit 15 of the micro-instruction).

5 The trigger 59 and the element AND-NOT 60 provide a stop in the T5 cycle when pressing the Reset button of the block 1.

Setting the trigger 58 to 1, i.e. continued work

0 is performed by pressing the Start button of the keyboard unit 1.

With the arrival of a low level signal generated by its HCl compression, a single vibrator circuit on elements 57, 66 and 67 produces a short negative pulse that directly triggers the trigger 58.

The trigger 58 is in a single state until the occurrence of a positive front from the output of the AND-HE element 64 when the stopping conditions appear.

Switch 4 (Fig. 6) is made on the basis of trigger 73, which is controlled by the fifteenth (youngest) word of RAM 15. The states of the direct and inverse outputs of the trigger 73 are switched through the elements 74 and 75 to the bus of the interface cards of the connected external device in the presence of an I / O command sign (PR.B-B) from the output of the decoder 3.

Unit 1 (Fig. 7) is structurally composed of a keyboard scanning circuit, an anti-debugging circuit, a control circuit, and a keyboard buffer register.

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The buffer register of the keyboard used in writing to RAM and setting the starting RAM address is performed on triggers 104-119. The write to the register is controlled by a circuit consisting of flip-flop 99, the item IS-NOT 100, counter 101, and decoder 103.

In the initial state, using the SVR.IND button. through the element OR NOT 102, the counter 101 is reset, thereby setting the highest bit of the register. Writing to it (O or 1) is performed by pressing the data buttons (0-7). The first time the signal is pressed, the trigger 99 is reset from the NAND 9L element and remains in this state until the last (sixth) press (i.e., until the entire buffer is full). By signal f} high level for an hour

Toto f, (500 kHz), the decoder 103 generates recording pulses on the trigger 104, as a result of which the lower digit of the digit code of the pressed button is written to the upper digit of the register,

After the button is pressed, the signal L disappears, the counter 101 goes out (in- cents) to the address of the upper triad of the buffer register, and the recording gates from the AND-HE element 98 are blocked. If the seventh click is mistakenly made, then re-writing to the buffer register is blocked by setting (set to 1) trigger 99 when the fill button for the lower triad of the buffer (i.e., to 117-119 triggers) is released with the sixth pressing.

Recording to RAM from block 1 is performed from the keyboard buffer register when the Record button is pressed (on a signal Recording from the output of the element OR NOT 79).

After pressing this button, the score is -. chik 13 increments. Similarly, the setting of the address of the counter 13 occurs when the button is pressed.

The keyboard scan pattern consists of a counter 76, a decoder 77, and an NAND 97 element.

The input element AND-NOT 97 is supplied

the interrogation frequency f 500 kHz from the built-in generator (frequency generator circuits f, and 4 are conventionally not shown) with which the keyboard buttons are polled.

When you press a button, a zero level signal appears at the input of an element

0

HE 86, calling up through the filter collected on element K-HE 87, cocking the flip-flops 90 and 95, as a result of which the frequency pulses f from the output of the IS-NE 97 are blocked and scanning stops. If the control button was pressed, then at the output of the element OR-HE 92 a signal 1 appears, allowing through the element HE 86 the passage of the corresponding signal from the control circuit of unit 1.

The state of the key is controlled by 5 anti-debugging circuits of frequency f

20

25

(Hz), the period of which is longer than the bounce time (3 ms).

When the button is released, the trigger 90 is reset first, and then. trigger 95. The reset of trigger 90 is effected by a signal from a single vibrator performed on elements 88 and 89. The frequencies f, and., are synchronized

The signal level b (resolution of writing to the keyboard buffer) of the high level of the elements OR NOT 96 is also blocked by pressing the control buttons. The outputs of the buffer register of the keyboard 30 (BRK ot) are connected to the input of the RAM 2 unit, and the inverse outputs of the flip-flops 105-110 (not shown) to the input of the counter 13.

invention formula

0

A channel simulator containing a command type decoder, a mode register, a main memory unit whose output is connected to the information inputs of the sample signal switch, an information register, an increment counter and the first information address address counter, the input block, the first output of which is connected. with the input of the record of the simulation program of the operative memory block, and the second output with the input of the start of the clock generator, a block of permanent memory, the output of which is connected to the inputs of the resolution of the write register of the operative address hydrochloric memory register receiving information register vschachi information, the RAM block - ti, the address counter RAM memory and the first bit information entry address the ROM counter discharge dnym second data input connected to the per5

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Claims (1)

ed claims A channel simulator containing a command type decoder, a mode register, a random access memory block, the output of which is connected to the information inputs of the sampling signal switch, information output register, increment counter and the first information input of the address counter, input block input, the first output of which. connected to the input of the recording program of the simulation of the RAM block, and the second output to the start input of the clock generator, a constant memory block whose output is connected to 50 ^{w of the} write enable address of the RAM address register, information reception register, information output register, RAM block , the RAM address counter and the first bit information input of the permanent memory address counter, the second bit information input connected to the first output of the increment counter, the first the information input of the random access memory block is connected to the output of the information reception register, the address input of the permanent memory block is connected to the output of the constant memory address counter, characterized in that, in order to reduce the hardware costs of the simulator, a comparison circuit, a readiness register and an interface signal register are introduced into it moreover, the output of the RAM block is connected to the first information input of the comparison circuit, the information input of the readiness register, the third bit information input of the address counter p memory and through a command type decoder with a control input of the sampling signal switch and a write permission input of a constant memory address counter, the fourth and fifth bit information inputs of which are connected respectively to the outputs of the comparison circuit and the readiness register, which controls the input connected to the count inputs of the counters of the operational and constant addresses memory, the output of the clock generator, the synchronizing inputs of the random access memory block, the reception and output registers of information and the interface register ignals, the information input of which is connected to the output of the permanent memory unit, the output of the information reception register is connected to the second information input of the comparison circuit, the information input and the output of the RAM address register are connected respectively to the output and the second information input of the RAM address counter, jq, the third information input of the connected to the second output of the input block and through the mode register to the input of the clock generator mode, the permitting input of which is connected to the output of the constant block pa They are the incremental counter of the increment counter, the second output of which and the output of the RAM address counter are connected respectively to the second 2Q information and address inputs of the random access memory block, the output of the switch of the sample signal, the group of outputs of the register for issuing information, the group of outputs of the register of interface 25 signals are the corresponding output and groups of outputs of the simulator for connection to the selection buses, input information buses and control buses of an external device, group 3θ of the inputs of the reception register information and readiness register are the corresponding groups of inputs of the simulator for connecting to the output information buses readiness buses of an external device. FIG. 3 φύ2.6 I 467 556 bo CM Yu φ V ^ i ₍ ca I V. <+ to \ | | si S Rj h Y ^ r XP δ ° c> SJ No.E | - ( - * rs g — s ) - + ► S * 3 ° ζ> Vv j !> - 1 "4 £ h "about h> * -s. GC. <o Ϊ h \ h'.Hh>x§>*> 4 * · e • n • ύί 2 = 1111 s> 5 ^e »§ 6 <51 l l § s. “^ 7 < l Cl to. ss h> S ’ Sz 'o about g t sous fro ss h> r— £ r / ' to ^x § TO l l L £> to ss? Q to> Q "Oh xx eh Ϊ— t s \ 1 frO 'λι ϊ H ". TO > h 7 U6 L Q about Q H> ¢ 3 <<> O <j to CM Y <u B, <\ | Xj. i *! \ e- tQ § Cc <t- g t si to zr Fs / g. 7 v * 43