SU1396279A1 - Frequency synthesizer - Google Patents

Abstract

The invention relates to the field of radio engineering and m. used in radar and radio navigation systems and communications technology. The purpose of the invention is to increase the spectral purity of the output oscillations. The device contains a reference r-1, a phase detector 2, a frequency divider with fractional coefficients. division 3, controllable, rr. 4, constant-voltage block (bfps) 5, low pass filter 6. At the same time, the BVPS 5 contains an adder 7 codes, A1 | P 8, memory registers 9, 13, multipliers of codes 10, 11, a block of weight cracks. 12, a DAC 14. The weighted processing of the output voltage of the phase detector 2 makes it possible to exclude the harmonics of the form from the output voltage spectrum of the synthesizer and thus reduce the level of side components in the output oscillation spectrum. 1 il. i SL with so O5 th so

Description

The invention relates to radio engineering and can be used in radar and radio navigation systems and communication technology.

The aim of the invention is to increase the spectral purity of the output oscillations.

The drawing shows a structural electrical circuit of a frequency synthesizer.

The frequency synthesizer contains a reference oscillator 1, a phase detector 2, a frequency divider 3 with a fractional division ratio (DDPK), a control oscillator 4, a constant selection unit 5 (BVPS). 6 low pass filter. The BVPS contains an adder 7 codes, an analog-to-digital converter (ADC) 8, the first memory register 9, the first 10 and second 11 code multipliers, a weighting factor block 12 (BVK), a second memory register 13, a digital-to-analog converter (IWI) 14.

The frequency synthesizer works as follows.

The frequency of the controlled oscillator 4 adjusts the constant component at the output of the phase detector 2, the oscillation spectrum at the output of which has a complex shape. In addition to the constant component, there are harmonics due to the sawtooth character of the voltage at the output of the phase detector 2. The parasitic deviation of the phase of the output oscillations of the controlled generator 4 is determined by the variable component of the output voltage of the phase detector 2. At the same time, the parasitic harmonics on The output of the phase detector 2 is a multiple of the frequency of the sawtooth voltage and the intensity of these harmonics is determined by the Fourier row coefficients. In addition, the shape of the sawtooth voltage varies with the frequency synthesized, and the constant component of the sawtooth voltage also changes. In order to improve the spectrum of the output oscillations of the frequency synthesizer, it is necessary to exclude harmonics from the spectrum of the output oscillations of the phase detector 2, for which the output signal of the phase detector 2 is fed to the second input of the BVPS 5. The ADC 8 starts at the times t, t, ... , t, determined by the frequency of the reference oscillator 1. Pere

The frequency switching in the phase-locked loop of the frequency occurs by changing the division ratio of the DCPD 3 over the time interval {t, i.e. over the period of the sawtooth voltage, the division factor (N + 1) is established several times and (n - K) times - the division factor. N, where n is the ratio of the period of the sawtooth voltage T to the frequency period of the reference generator 1 TC ,.

P

t h - to

-i-t-1

- t

foCth - to).

where fg is the frequency of the reference oscillator 1.

The instants t to switch the division factor are determined by the frequency code supplied to the DCPD setup outputs 3. The instant that the division factor is changed from. (N + 1) at N corresponds to the maximum of the sawtooth voltage at the output of the phase detector 2. Parallel voltage codes A, - from the output of the A / D converter 8, are fed to the first multiplier 10, where signals 1 are simultaneously fed from BVC 12.

The weighting factors 1, recorded in BVK 12, are determined in accordance with the shape of the sawtooth voltage at the output of the phase detector 2 at different frequencies for all operating frequencies and can be calculated by the formula

K, ,

  1 to

J-

0

five

0

five

one;

P - K

 2 (pt)

i К + 1, ..., p-1,

where n is the number of counts during the sawtooth period; K is the number of counts from the initial point of the sawtooth period to its maximum. BVK 12 can be configured as a counter of two permanent storage devices (not shown), one of which stores weighting factors for all operating frequencies, and another constant storage device stores tables of weighting factors (1 - Ij). If we successively address with a counter at known addresses, a table of weights for the selected frequency is obtained at the outputs of the permanent storage devices. The initial installation of the counter is done

at times tg pulses from the DCPD output 3. The start address in BVK 12 is set from the setup input, and this address determines the number of the weighting factor table (the selected frequency). The switching of the counter in the BVK 12 is effected by pulses from the reference generator 1.

At the output of the first multiplier 10 receive the product A-1. The countdown of voltage A at the beginning of the sawtooth period at the time tp by the command from the DPDK 3. is remembered in the second register 13, and then multiplied in the second multiplier 11 by the coefficient (1-1c). At the output of the second multiplier 11 get the product A, (1 - 1,). The products of the codes, - and AO (I, - 1;) are fed to the input of the adder 7, at the output of which a set of codes is obtained, described by the formula

L AO + (A; - AO)

one.

In view of the expression for 1, the following numbers are obtained at the output 25 of the adder 7:

; - | t- (A, -A,) + A «, i 1К;

) ,,

  Vп - 1.

This formula determines the sampled values of the constant component L- of the sawtooth voltage at the output of phase detector 2. Numbers b. request

In the first, register 9 and in the DAC are transformed into voltage, which through the filter 6 controls the controlled generator 4.

Thus, the weighting treatment of 40 voltages of the phase detector 2 makes it possible to exclude from the spectral voltage of the synthesizer from the harmonic of 1-1 d and thus reduce the level of side components in the spectrum of the output bath. rm l l from gaining

Frequency synthesizer, containing sequentially connected filter bottom-50

Compiled by Y. Kovalev Tehred LS Serdyukova

They were divided by the output ratio of the output key for the output filtering of the key file, which was radically compared to the first one of the team, which was in tact with the unit with a hundred digits of the second ring. dark dark blockade.

actor E. Kopcha

0

five

0

five

0

five

0 5

0

these frequencies, a controlled oscillator, a frequency divider with a fractional division factor and a phase detector, as well as a reference oscillator, the output of which is connected to the second input of the phase detector, and a DC selection unit, the first and second inputs and the output of which are connected respectively to the second a frequency divider output with a fractional variable division factor, a phase detector output and a low-pass filter input, characterized in that, in order to increase the spectral purity of the output signal, the third input the DC allocation unit is connected to the output of the reference oscillator, and the DC allocation unit is designed as a series-connected analog-to-digital converter, the first code multiplier, a code adder, the first memory register and a digital-to-analog converter, while the output of the analog the digital converter I is connected to the second input of the code adder via a second memory register connected in series and a second code multiplier, the first output of which is connected to the second input of In this case, weighting coefficients, wherein the clock input of the second memory register is combined with the control input of the weight coefficient unit and is the first input of the DC allocation unit, the input of the analog-digital converter is the second input of the allocation unit of the DC component, The second input of the first code multiplier is connected to the second output of the weighting factor block, the clock input of which is combined with the clock input of the analog-digital converter and is the third input of the allocation unit constant The output of the digital-to-analog converter is the output of the dc block.

Corrector I. Muska

Claims (1)

Claim A frequency synthesizer containing frequencies based on them, a controlled oscillator, a frequency divider with a fractionally variable division coefficient and a phase detector, as well as a reference oscillator whose output is connected to the second input of the phase detector, and a DC component isolation unit, the first and second inputs and output of which are connected respectively to the second output of the frequency divider with a fractionally variable division coefficient, to the output of the phase detector and to the input of the low-pass filter, characterized in that, in order to increase spectral purity of the output signal, the third input of the DC component allocation unit is connected to the output of the reference generator, and the DC component extraction unit is made in the form of a series-connected analog-to-digital converter, first code multiplier, code adder, first memory register and digital-to-analog converter, while the output is analog-to-digital converter | is connected to the second input of the code calculator through a second memory register and a second code multiplier connected to the second input of which the first output of the block of weight coefficients is connected, while the clock input of the second register of memory is combined with the control input of the block of weight coefficients and is the first input of the block of separation of the constant component, the input of the analog-to-digital converter is the second input of the block of selection of the constant component, the second input of the first code multiplier is connected to the second output block weight factors, the clock input of which is combined with the clock input of the analog-to-digital converter and is the third input of the unit and allocating the dc component, the output digital to analog converter is a constant output of the isolation filter connected sostavlyayusledovatelno LO-50 conductive.