SU1494215A1 - Digital frequency synthesizer - Google Patents

Abstract

The invention relates to radio engineering. The purpose of the invention is to increase the uniformity of the step of the grid of synthesized frequencies. The synthesizer contains a controlled r-r 1, a mixer 2, a multiplier 3 frequencies, dividers 4 and 5 frequencies with variable coefficients. division, a pulse-phase detector 6 and a low-pass filter 7, forming a phase locked loop, and D - trigger 8, multiplexer 9, and sensors 10 and 11 codes. Setting the digital codes of the divider 4 and sensors 10 and 11 provides a uniform grid of frequencies in the synthesizer with a relatively large number of synthesized frequencies. The frequency grid spacing can be made small while maintaining a high rate of reorganization of the synthesized frequencies. In the output signal, there are no side components associated with the quality factor. division, because the sequence of output pulses of divider 5 is strictly uniform. The goal is achieved by introducing a divider 4, D - trigger 8, multiplexer 9 and sensors 10 and 11. 1 Il.

Description

4: CO 4 GO

SP

31

The invention relates to radio engineering and can be used to generate a grid of frequencies in radio receiving and radio transmitting devices.

The purpose of the invention is to increase the uniformity of the step of the grid of synthesized frequencies.

The drawing shows a digital frequency synthesizer.

The digital frequency synthesizer contains a controlled oscillator 1, a mixer 2, a frequency multiplier 3, a second 4 and a first 5 frequency dividers with a variable division factor (DPD), a pulse-phase detector (IFD) 6, a low-pass filter 7 (LPF) 7, D -trigger 8, multiplexer 9 and the first 10 and second 11 code sensors.

Digital frequency synthesizer works as follows.

The signal from the output of the first DPCD 5 is fed to the input of the setup in the D-flip-flop 8 and sets it to the zero state. The signal from the direct and inverse outputs of the D-flip-flop 8 sets the multiplexer 9 to the position when the digital input code k from the output of the first sensor codes 10 is fed to the control input of the second PDCD 4.

but

to the input of the first DCPD 5 and

154

the code at the output of the first sensor 10 coding n - the digital code at the output of the second sensor 11 N codes - the digital installation code of the first DPCD 5). Then the period of the output signal of the first DPCD 5

 Dfcd f

APKD

G7CH

 ",; (F 01

get

k-n

  f APKA ("+ ----) + f

Oi

where f y, is the output frequency of the controlled oscillator 1, f-01 is the offset frequency.

Since in the steady-state mode, the phase-locked loop of the frequency formed by the controlled generator 1, mixer 2, frequency multiplier 3, DPDK 4 and 5, IFD 6 and LPF 7, f Ups f 2 (I fle f 02 is the reference frequency of the digital frequency synthesizer), that

f b., to fot (N - -) f.

house

In this way for

the clock input of the D-flip-flop 8 from the output of the second PDCD 4 receives a pulse that converts the D-flip-flop 8 to the unit state, and the signal from the direct and inverse outputs of the D-flip-flop 8 switches the multiplexer 9 to the position where the input of the second PDKD 4 receives the digital code and from the output of the second 11 sensor codes; in this case, the input of the first DPK 5 and the clock input of the D-trigger 1 from the output of the second DPCD receives a periodic signal from the period-Tp1P

one period of the output frequency of the first PDCD 5, its input receives N periods of the input frequency, one of

T pm k / h (N-1)

P

(where T is the repetition period of the signal at the output of the mixer 2; k is the digital

which value

Periods matter

The sequence of the output pulses of the first DPCD 5 is strictly uniform, therefore, the side components associated with the fractionality of the division factor in the output signal of the digital frequency synthesizer are absent.

The output frequency step is equal to

f

07

(-)

If it is necessary to obtain an output frequency that is a multiple of the reference frequency f gjt, the installation code of the first sensor 10 k codes is equal to n. The output frequency of the digital frequency synthesizer f oi

If it is necessary to obtain an output frequency that is not a multiple of the reference frequency, the code k takes values that are not multiples of the code of the code. In this case, for k: n, the grid step of the digital frequency synthesizer takes negative values, and for positive, when k O, the output frequency

fBi, (N-l) + f

01

The number of synthesized frequencies with a fixed value of N and the value of Oh k f; n is equal to (n + 1).

Since the input of frequency multiplier 3 is a frequency equal to

ffccc frequency multiplier 3 can operate with sufficiently large n, limited only by the speed of the second DPCD A and the tuning range of the output frequencies of the digital frequency synthesizer.

Thus, the digital frequency synthesizer provides a uniform grid of frequencies, with a relatively large number of synthesized frequencies. The grid spacing of a digital frequency synthesizer can be made small while maintaining a high speed of tuning the synthesized frequencies.

In addition, in the output signal of the digital frequency synthesizer there are no side components associated with the quality factor of the division factor, since the sequence of output pulses of the first PDCD 5 is strictly run-dimensional.

Claims (1)

Invention Formula A digital frequency synthesizer containing serially connected first frequency divider with a variable division factor, pulse-phase 942156 A second detector, a low-pass filter, a controlled oscillator and a mixer, as well as a frequency multiplier, characterized by h-v :), with the help of increasing the uniformity of the grid pitch of the synthesized frequencies, a multiplexer, a second frequency divider with a variable division factor, D-trigger , as well as the first and second code sensors, the direct and inverse outputs of the D-flip-flop being connected respectively to the first and second control of the 1M inputs of the multiplexer, the first and second code sensors are connected respectively to the first and second signal inputs ultiplekso- pa, whose output is connected to the control input of the second frequency divider with a variable coefficient dele10 15 20 No, the mixer output is connected to the input of the multiplier often, the output of which is connected to the input of the second frequency divider with a variable division factor, the input of the D-flip-flop setting to the output of the first frequency divider with a variable division factor, the output of the second frequency divider with a variable division factor connected to the input of the first frequency divider with a variable division factor and the clock input of the D-flip-flop, the D-input of which is the input of the signal of the logical unit, the other input of the mixer is -; This is the input of the offset frequency signal.