SU1497703A1 - Digital frequency synthesizer - Google Patents

Abstract

The invention relates to radio engineering. The purpose of the invention is to reduce the tuning time from frequency to frequency. The synthesizer contains a setting unit 1 for the frequency code, a calculating unit 2 for the current phase, a converter for 3 phases to amplitude, a DAC 4, low-pass filters 5 and 8, a matching unit 6, a phase discriminator 7, a controlled oscillator 9 and a reference oscillator 10. At In this calculation block 2 contains counters 11 and multipliers 12 codes. The generator 9, encircled by a phase locked loop, generates a continuous pulse train that enters calculation block 2. Here the code of the current signal phase is formed, which is then converted into a corresponding digital sine wave sample. The code of this sample is fed to the DAC 4 and then filtered in the operating frequency band by filter 5. The tuning time from frequency to frequency is mainly determined by the passband of filter 5, and to recover a time-sampled pulse signal, its passband must be no more than half the sampling rate i.e. oscillator frequencies 9. With real filters, the bandwidth should be about a quarter of that frequency. 1 il.

Description

The invention relates to radio engineering and can be used in radio receiving and radio transmitting devices to obtain a grid of stable frequencies.

The purpose of the invention is to reduce the tuning time from frequency to frequency.

The drawing shows a structural electrical circuit of a digital frequency synthesizer.

The digital frequency synthesizer contains a block 1 for setting the code of the frequency block 2 for calculating phase tekupey, a converter for phase 3 amplitude, a digital-to-analog converter (PAP 4, first fil1) Tr 5 low frequencies, a matching element 6, a phase discriminator 7, a second low-pass filter 8, control generator 9, alternator 10. Calculation unit 2 contains N counters 1 1 i-1, N mind I 1

N

scissors 12, - 12. codes.

Digital frequency synthesizer works as follows.

The controlled generator 9 generates a continuous sequence of pulses, which is fed to the counting inputs of the counters 11, - 11 of the calculation unit 2. Each of the N counters 11–11 counts the number of clock pulses modulo Codes with the output of counters 11 are fed to the inputs of the corresponding multipliers 12, –12, codes, to the second inputs of which the code of the synthesized frequency is fed from block 1 to set the code. As a result of multiplying these codes in mutually simple modules, the outputs of multipliers 12 form a code for the current phase of the signal, which is fed to the inputs of a 3-phase converter, for example, a fixed memory or a logic matrix, where it is converted into a corresponding digital sinusoid sample. The digital sampling code is applied to CAC 4, the output voltage of which is filtered by filter 5 in the operating frequency band.

-

ten

15

20

25

thirty

35

N P i 1

where f is the frequency of the controlled oscillator 9;

the product of the modules of the recalculation coefficients of counters 11, - 11 block 2 imprints, i.e. determined by the clock frequency

pulses.

The controlled oscillator 9 is covered by a phase locked loop which includes a reference generator 10, a phase discriminator 7, and a second filter 8, and the frequency dividers in the phase locked loop use counters 11, 11 of the calculator 2, the outputs of which are through element 6 the match is connected to another input of the phase discriminator 7.

With this implementation, the frequency divider of the phase locked loop

its division factor is equal to PR.

iti

The tuning time from frequency to frequency is mainly determined by the passband F of the first filter 5, and to restore a time-sampled pulse signal, its passband must be no more than half the sampling rate, i.e. frequency controlled oscillator 9.

For real filters, the bandwidth should be about a quarter of that frequency.

one

40

In view of (1)

P P.Af

Accordingly, the switching time determined mainly by the passband of the first filter 5 is

50

Per

The frequency tuning step of the synthesizer is determined by the expression

f t

(one)

ETC,

Claims (1)

Invention Formula A digital frequency synthesizer containing a reference oscillator, a frequency code setting unit and a current phase calculating unit connected in series to a phase to amplitude converter, a digital-to-analog converter and a first low-pass filter are distinguished by the fact that, in order to reduce the tuning time from frequency to frequency, they are entered sequentially the coupled match element, the phase discriminator, the second low-pass filter and the controlled oscillator, and the current-phase calculation unit is executed in the form of N channels, each of which consists of a series-connected counter and smart 5 "5 code bits, the outputs of each of the N code multipliers are connected to the corresponding transform inputs Phase-to-amplitude bodies, the setup inputs of each of the N code multipliers are connected to the corresponding outputs of the frequency code setup block, the counting inputs of each of the N counters are combined and connected to the output of the controlled oscillator, the output of each of the N counters is connected to the corresponding inputs of the matching element, and the output of the reference generator is connected to another input of the phase discriminator; in each of the N channels, the counter module is equal to the code multiplier module and is mutually simple with respect to the counter module dogo of N channels.