SU1379779A1 - D.c. voltage stabilizer - Google Patents

Abstract

The invention relates to electrical engineering. The goal is to increase speed and reliability. For this purpose, an adder 9 and a decoding unit 8 are inserted into the stabilizer. The output voltages of the converter modules (it) 1,2,3,4 are summed and fed to the output of the stabilizer. The error signal from the output of the measuring unit 7 (IB) is fed to the first input of the adder 9, the second input of which is supplied with the synchronizing voltage from the output of the generator 6. The total signal from the output of the adder 9 is fed to the input of the analog-1 converter of the ADC 5, and the second input of which The clock signal is received from the second output of the generator 6. Signals from the output of the A / D converter 5, containing information both in the form of a code and in time, are fed to the inputs of the decoding unit, which converts the signals of the A / D converter 5 into conversion control signals nazal modules 1, 2, 3, 4, which determine the number of switched on converter modules and the fill factor of the pulse pulse modulator — a signal from the control of the PM 4 loop. 2 Cp. files, 10 ill. (ABOUT

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The invention relates to electrical engineering, in particular to secondary power sources, and can be used to stabilize a high level of constant voltage.

The purpose of the invention is to increase speed and reliability.

Fig. 1 is a structural diagram of a constant voltage stabilizer; figure 2 - diagram of the analog-to-digital Converter with the conversion of the output information with respect to the input code Johnson; on fig.Z - diagram of the measuring unit; figure 4 - diagram of the adder; FIG. 3 is a diagram of a decoding unit on a parallel register and multiplexer; figure 6 is the same on the parallel register, digital comparator and logic circuit OR; Fig. 7 illustrates a converter module for implementing two on-off states; in fig. 8 - the same day control of the pulse width modulator of the PWM signals; Fig. 9 shows diagrams for the operation of the device; Fig. 10 is a table of correspondence of input and output signals of a decoding unit.

The stabilizer contains constant-voltage constant-to-voltage converter modules (PM) 1-4 with control inputs, an analog-to-digital converter (ADC) 5 with conversion of output information with respect to the input by Johnson code, generator of 6 control pulses (GNU ) and the measuring unit (IB) 7, and PM 1 - 4 at the entrance are connected in parallel, and the output in series. The decoding unit 8 outputs connected to the control inputs PM I - 4, and the inputs connected to the outputs of the ADC 5, the input of which is connected to the output of the adder 9, the inputs of the latter with the outputs of GNU 6 and IB 7. The clock input of the decoding unit 8 is connected to the output of GNU 6 .

The PM consists of the key 10, the master oscillator 11, the power amplifier 12, the center of the miter 13, the filter 14. The control parameter of the BAT signal after the key 10 is the LCD filter 15.

The stabilizer works as follows.

When applying to the input of a stabilizer of direct voltage, PM 1 - 4 start working. Modules 1 - 3 (Fig.7)

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contain a serially connected control switch 10, a master oscillator 11, a power amplifier 12, an expander 13 and a filter 14. The base of the control key 10 is a control input PM 1 - 3. PM 4 (Fig. 8) differs from the presence of an LCD filter 15 between the control key 10 and the remaining PM elements. Due to this, PM 4 can be controlled by a 111M signal. The output voltages III due to the series connection of their outputs are summed up and fed to the input of the stabilizer. IB 7 (FIG. 3) generates at the output a misalignment signal between the output and the reference voltages.

Mismatch signal from the output

0 IB 7 is supplied to the first input of the adder 9, the second input of which is supplied with the synchronizing voltage from the first output of the GNU 6. According to one of the possible construction options, the adder 9 (Fig. 4) is a differential amplifier, the input A being used to provide the error signal and input B is for synchronization signal. The total signal from the output of the adder 9 is fed to the input of the AIP 5, the second input receives a clock signal from the second output of the SMI 6. The synchronizing voltage of the SMI 6 can be symmetrical

5 and asymmetrical sawtooth, as well as exponential with acceptable curvature. The clock signal is a sequence of square pulses of the same frequency as the clock voltage frequency, having a constant phase delay Q relative to the latter, necessary for normal operation of the ADC 5.

The signals from the output of the ADC 5, containing information both in the form of a code and in time, are fed to the inputs of the decoding unit 8. It converts the signals of the ADC 5 into signals

0 control PM I - 4, which determine the number of included W 1 - 3 and the fill factor of the PWM control signal PM 4. Thus, the feedback is closed.

ADC 5 (FIG. 2) consists of four voltage comparators, the first inputs of which are connected together and form the input of the ADC 5. The other inputs of the comparators are connected to after

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connected by resistors R, through which current flows from current source I. In this case, the voltage across the first resistor, equal to IR, is the reference voltage of the first comparator K1, the voltage drop across the second resistor 2 IR is the reference voltage for comparator K2 and t The control algorithm of the PM is determined by the structure of the decoding unit 8 and is explained with the help of Fig.9, which shows the levels of the reference voltages and "", 1R; and „„, 2IR; and „,, 3IR; and ,, „, 4IR and four characteristic values of the output signal of the adder 9. The signal from the output of the adder 9 O U: Ujn means that the comparators K2 - K4 are at the outputs of the logic voltage O, and the output of the comparator K1 has a sequence of rectangular pulses with a fill factor proportional to the error signal. If Uon, Uj Uooi, the K3 and K4 comparators have a logic voltage O at the outputs, K1 - a logical 1, and K2 - a sequence of square pulses with a fill factor proportional to the error signal. Similarly, signals are produced at the outputs of the comparators in the cases when Ujn and: and cf. At this time, the sweep of the synchronizing voltage should be a little less than I-R, usually and (0.99-0.95) IR.

The signals X, XX, X d from the output of the ADC 5, counted at the time of the clock signal, are combinations of the Johnson code: 0000, 1000, 1100, 1110, 1111. It should be noted that such combinations are the simplest ADCs, and they are: decoding using a decoding unit to control signals, the PM requires the least amount of hardware. In addition, when using the Johnson code, such a structure is expanded by the following rule without restrictions. These signals are converted by the decoding unit 8 into control signals PM 1-4 (Fig. 9). PM 4 operates in a pulse-width adjustment mode, and PM 1–3 is switched on discretely. The decoding unit is a synchronous serial logic circuit, pre / 9779

forming the output signals of the ADC to the control signals PM. Circuits are characterized by a number of internal, early states encoded by internal variables. The signals recorded at the time of the occurrence of a clock signal are selected as such variables in the decoding unit. A parallel register or individual synchronous D-flip-flops can serve as a memory element.

The truth table of FIG. 10 characterizes the correspondence of the control signals t5 of the PM YI-Od with the output signals of the ADC X, - X and the internal variables X, - X /. From the analysis of the circuit diagram of the decoding block (figure 5) using the standard 0 16-input multiplexer, it can be seen that YI is Xg, Y, X, YX 4, and Y, X, Xj-m, where m are the internal minterms variables; i 1,3,7,15 - numbers of minters - 5 mov.

The i-number of the minter determines the number of the information input of the multiplexer, to which the corresponding signal of the ADC X must be applied, with 0 this i is 1. The internal variables are used to address the information inputs of the multiplexer. Another variant of the construction of a decoding unit (Fig. 6) is characterized by the use of a binary code comparator to form a signal Y ,. As can be seen from FIG. 10, Y, I if and only if the code is X X, Xjx X},. The Q value of the signals of the A / D converters is applied to the inputs of the comparator of the number A, and the internal variables to the inputs of the number B. The outputs of the comparator A B and A B are connected to the inputs of the OR logic circuit. 5 In the stabilizer, the probability of faultless operation is equal to the probability of faultless operation of a single PM with one or several redundant PMs, fast1X} the action is equal to Qd, since the feedback signal goes to all control inputs of the PM simultaneously.

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Claims (3)

1. A DC voltage stabilizer containing converter modules connected in parallel to the input and after the output 51 An analog-to-digital converter that converts the output information with respect to the input by Johnson code, a control pulse generator, a measuring unit, inputs connected to the output pins, distinguishes DI and сs in order to improve speed and reliability , an adder and a decoding unit are entered into it, with the outputs of the decoding unit connected to the control inputs of the converter modules, and the inputs to the outputs of the analog-to-digital converter with the conversion of the output information with respect to Johnson code input, the input of which is connected to the output of the adder, whose inputs are connected respectively to the first step of the control pulse generator and to the output of the measuring unit, and the clock input of the decoding unit is connected to the second output of the control pulse generator. 2. The stabilizer of claim 1, wherein the decoding unit is implemented as a parallel register and a multiplexer, the information inputs of the register being the inputs of the decoding unit and connected to the information inputs of the multiplexer, whose address inputs are connected to exits the parallel register, the multiplexer output is the first output of the decoding unit, and the second, third, and fourth outputs of the parallel register are the subsequent outputs of the decoding unit, and the clock input of the parallel register is the clock input of the decoding unit. 3. The stabilizer according to claim 1, characterized in that the decoding unit (the unit is made in the form of a parallel register and a digital comparator and an OR logic element, the first group of inputs of the digital comparator being connected to the information inputs of the parallel register block, and the second group of inputs of the digital comparator is connected to the outputs of the parallel register, the inputs of the logic element OR are connected to the outputs of the equality of codes and the excess code at the input of the parallel register with respect to the code at its output, respectively, the OR output of the logical element is the first output of the decoding unit, and the second, third and fourth outputs of the parallel register, with the exception of the first, are the subsequent outputs of the decoding unit, and the clock input of the parallel register is the clock input of the decoding unit . Puzt R - ± Fig. 3 and a b ont d j and Corner 1