SU1386973A1 - A.c. voltage calibrator - Google Patents

Abstract

The invention relates to secondary power sources of radio equipment. The aim of the invention is to increase the accuracy and increase the discreteness of the output voltage level setting. This goal is achieved by introducing a synchronous detector 10 together with the polarity determiner 11 into the device, comprising an inverter AC-to-constant voltage converter as well as serially connected pulse counter 7, a code comparison node 8, an adder 9, implemented together with Converter 6 of the code in the time interval multi-cycle formation of the control signal. The input code is represented as an integer part, the input to the input of the code comparison node 8. The number of averaging cycles is determined by the capacity of the counter 7 pulses. 2 Il. with b (L with

Description

oo

CX)

and with

with

Fig. /

eleven

The invention relates to electrical engineering and can be used in the construction of high-precision sources of alternating voltage for information-measuring systems.

The purpose of the invention is to increase the accuracy and discreteness of the output level setting.

Figure 1 shows a block diagram of a variable voltage calibrator; on - functional synchronous detector circuit.

The ac voltage calibrator contains a series-connected voltage source 1, a key 2, an integrator 3, an analog storage unit 4, a controlled oscillator 5 connected to the output terminal, and a code converter 6 in the time interval connected to the control input of the key 2, as well as sequentially connected to the output of the converter 6 of the code in the time interval counter 7 pulses, node 8 comparison of codes and adder 9, the output connected to the input of the converter 6 of the code in the time interval, and the second input of the connection with the output for connecting the control signal source, while the output for connecting the additional control signal source is connected to the second input of the code comparison node 8, and the pulse output of the pulse counter 7 pulse is connected to the control input of the analog storage node 4 and also connected between the output device and the second input of the integrator 3 synchronous detector 10 polarity identifier 11 connected to the output of the analog storage node 4 and to the control input of the synchronous detector 10.

The adder 9, the counter 7 pulses and the node 8 comparison codes can be performed by any known schemes based on similar functional purpose of the logical elements of the type 155ИМЗ, 155И77 and 134СП2, respectively. The output signal of the code comparison angle corresponds to the level of the logical unit, if the code at the output of the pulse counter 7 does not exceed the control code Y from the source of the additional control signal Adder 9 is used to sum the input control code X with the control signal source c

.-

ten

25

35

40

the logical signal at the output of the node 8 comparison codes. The sampling signal TK to the analog storage unit 4 is generated by the sampling signal from the output of the pulse counter 7 once per cycle of operation of the device, the duration of which is determined by the capacitance of the pulse counter 7.

The synchronous detector 10 (Fig. 2) consists of a weighting resistor 12 and keys 13 and 14, controlled by signals from the output of a logic circuit of a synchronous detector consisting of two

15 comparators 15 and 16, two single-oscillators 17 and 18, trigger 19, element 2И-OR 20 and inverter 21. Comparators 15 and 16 and respectively one-oscillators 17 and 18 are designed

20 to form the leading and trailing edges of the key control pulses, the phase relation between the alternating direction signals and the key control signals fed to the element 2I-OR 20 is specified from the polarity determiner 11. The keys 13 and 14 are controlled by phase forwarding, then when connecting the output of the synchronous detector to the current input of the integrator 3, a constant input resistance of the synchronous detector is provided. The mutual adjustment of the comparators 15 and 16 makes it possible to reduce the errors of the synchronous detector 10 from the influence of noise at low signal levels.

The polarity determiner 11 can be made on the basis of an integral comparator of the type 521 CASE. As comparators 15 and 16 of a synchronous detector, it is necessary to use faster-acting comparators of the type 521CA4.

thirty

The comparator operates cyclically. The cycles are set by sampling pulses to the analog storage node 4. During the cycle, integrator 3 compares the volt-second areas of the signal from the source 1 of the reference voltage supplied to the input of the integrator 3 via key 2 and the feedback signal coming from the output of the device through synchronous detector 10. The non-compensated signal thus generated is accumulated on integrator 3 during a series of successive cycles, the number of which depends on the settings of the device.

stored by the analog storage unit 4 on the signals of the sample TZ and serves as a control signal for the controlled oscillator 5.

The time interval T1, controlling the keys 2, is formed by the code converter 6 in the time interval once per cycle of operation of the device T2, constituting ha of alternating voltage periods T (in the proposed and known calibrators), and is given by maximum value, cax must exceed tt

.

A sampling pulse TK is generated once in d clock cycles according to the selection signal-2Q ki of the pulse counter 7, for which the input counting signal is the clock pulses from the output of the code converter 6 in the time interval, and also I1 pulses themselves can be used.

The input control code N can be represented as an integral part of X, corresponding to the most significant bit of the code, and a fractional part of Y, represented by Q least significant bits of the code

N X- + Y / d,

where Y / d is the weight value of the lower

code bits. You can write down the identity

N

(X + 1) Y + X (d-Y) X

 X + Y / d, (3)

which indicates how to implement the above mixed number representation in this device. The required value of the control action corresponding to the N code can be obtained by averaging over the d cycles of a sequence consisting of the control signals defined by the codes X and (X + 1) for (d-Y) and Y cycles, respectively.

In this device, part of the input code N is fed to the input of the adder 9, which implements the code increment operation (X + 1) depending on the code value at its second input O or 1, which is given by the output signal of the code comparison node 8. The inputs of the node 8 comparison codes pos

,

d

15

the fractional part code Y is blunt, and the current code from the output of the counter is 7 pulses

Ncr A logical unit signal is generated, provided

NCT Y.

Suppose, then, in the initial state at 0, at the output of node B, a signal from Log.1 is formed, and the code CX + 1) arrives at the input of the code converter in the time interval, which is converted to the time interval

T (X + 1) (X + 1) T

(four)

where TD is the period of the clock frequency.

When the code N, Y is reached, the output of the adder 9 establishes the signal Log.O and during the subsequent (d-Y) cycles the time interval T XT, is formed.

When averaging over d cycles we get the average value of the time interval

T1sr

T (X + 1) T + (TX (d-Y)

(2)

- t (X + 1) Y + X (d-Y) „1 (5)

Using the introduced definition T1co and the corresponding value of the operation cycle of the device TC dT dmT (.., we can formally describe the iterative process of setting the output voltage of the calibrator.

After n cycles have elapsed after changing the control code N and, accordingly, T1j.p, the average value of the output voltage of the calibrator is

EoTlcp K, C

K.KS and Q and

i-

Wed about

Q (6)

where e,

K, K,

R ,, C

- voltage reference source;

- transmission coefficients of the analog storage unit 4 and the controlled generator 5;

- parameters of the integrator defining elements

3 at the input of the reference voltage source;

51386973

Uji. - initial value of the output voltage of the calibrator, h

Consider

, j-i

as sum

l p

j

members of a geometric progression with n members and a denominator

Q 1 - | | - - (7)

de 3 is the conversion coefficient of the synchronous detector 10; R - weight resistance

resistor 12 of integrator 3 at the input of synchronous detector 10,

you can simplify the expression (6)

EoT1c Ra

- -

(1-q) +

(eight)

To ensure the convergence of the iterative process, the following is established: (Q 1, then the steady state value; the output voltage of the calibrator of the calibrator 00 cycles is equal to

Ilcl

B R,

thirty

rtc

Nto. R2 pTc 17

maintaining a constant 35

(9)

25

Neither U |, p in the frequency range is required to maintain a constant value of the ratio T1cr / TC or TD / TC, which makes it necessary to monitor the frequency of the alternating voltage 1/1, .. In the case of building a controlled oscillator -5 based on a digital oscillator, performing a multiple conversion of the reference frequency, the problem is solved simply because a common master oscillator can be used for the controlled oscillator 5 and the converter 6 of the code in the time interval.

Then the expression (9) takes the form

N

about ftdmNc

R7

 RT

(ten)

N

- the multiplicity of formation of the output signal of the controlled oscillator 5 in frequency ().

Thanks to the proposed algorithm for operating the device, the discreteness of the code converter 6 in the time interval in the entire channel of the formation of the reference signal can be reduced d times, which will expand the operating frequency range and increase the linearity of the formation of the reference signal. Averaging the reference and feedback signals makes it possible to reduce Bj times the effect of random errors in the formation of these signals.

five

0

0

five

Depending on the sign of Q, the transient setting of the output voltage can be oscillatory () or monotonic (). With large changes in the output signal, the voltage on the integrator 3, and consequently, on the output of the analog-jBoro storage node 4, may change sign. In this case, to achieve absolute stability of the calibrator, it is necessary to ensure that the joint characteristic is odd. converting the blocks between the output and the input of the integrator 3, in this case, the analog storage node 4, the controlled oscillator 5 and the synchronous detector 10. At least the last two blocks may have characteristics insensitive to the polarity and phase of the input voltage, t . tend to respond only to an input voltage module. The required transformation of the Joint characteristic of the blocks implements the polar identifier 11 together with the logic circuit of the synchronous detector 10, consisting of the element 2I-I1PI 20 and the inverter 21. The polarity of the output signal of the synchronous detector 10 corresponds to the polarity of the voltage at the output of the analog storage node 4.

0

45

50

55

Claims (1)

Invention Formula An ac voltage calibrator containing a series-connected reference voltage source, a key, an integrator, an analog storage node and a controlled oscillator whose output is connected to the output terminal, and a code converter in the time interval whose output is connected to the input / G 8bi; fody yc / 77poucfnSa g 15 17 ch to block n Editor A. Kozoriz C} and d. 2 Compiled by S. Chernysheva Tehred M. Khodanich Proofreader N. Korol fz / lokuz go one. 2G