SU1424128A2 - Regenerator of quasiternary digital signal - Google Patents

Abstract

The invention relates to communication technology. The purpose of the invention is to improve noise immunity. The regenerator contains the amplifier-corrector 1, the control unit 2, the driver 3 of the control voltage, r-4, frequency divider 5, the output unit 6, controlled filters 7 and 8, the low-frequency amplifier 9, the adder 10, el SPARKET - PARTITOR OR AND, averaging block 12, comparators 13 and 20, blocks of match 14 and 16, inverter 15, reversible counter 17, DAC 18, controllable delay block 19 and r-r 21 pulses, If for any reason the clock pulses are shifted to the right (left) of their optimal position, then in the device the reduction (increase) is carried out The clock pulses are output from the delay block 19, which is ensured by the operation of the reversible counter 17 in the forward (reverse) counting mode. The goal is achieved by improving the accuracy of clock phasing. 2 Il. About in (P

Description

The invention relates to communication technology, can be used in digital information transmission systems and is an improvement of the regenerator according to ed. St. No. 1022316.

The aim of the invention is to increase noise immunity by increasing the accuracy of phasing of clock pulses. 10

In FIG. 1 shows a structural electrical diagram of a regenerator of a quasi-digital signal; in FIG. 2 is a timing diagram of the operation of a 'regenerator. fifteen

The regenerator contains amplifier corrector I, control unit 2, control voltage generator 3, generator 4, frequency divider 5, output unit 6, first controlled filter 20 7, second controlled filter 8, low-frequency amplifier 9, adder 10, EXCLUSIVE OR 1I element, block 12 averaging, first comparator 13, first coincidence unit 14, 25 inverter 15, second coincidence unit 16, counter 17, digital-to-analog converter 18, controlled delay unit 19, second comparator 20, pulse generator 21. thirty

The regenerator of a quasi-digital digital signal operates as follows.

A quasi-ternary digital signal, as well as a synchronizing sinusoidal signal 25, is introduced into the low-frequency part of the spectrum of the digital signal, and the frequency of the sinusoidal signal is several times less than the clock frequency of the digital signal. The synchronizing sinusoidal signal is suppressed in the amplifier-corrector 1, and the corrected information signal is supplied to the first input of the control unit 2. Using a controlled filter 45, a sinusoidal signal! Is extracted and fed to the second input of the control unit 2, and also, through the low-frequency amplifier 9, to the input of the adder 10. From the two information outputs of the control unit 2 there are two flows of rectangular pulses corresponding to positive and negative pulses of a quasi-ternary signal are fed to output block 6. From the output of block 6, a quasi-tropic signal, in the spectrum of which a frequency section is cut out for transmitting a sinusoidal signal using a controlled filter 8, steps on the other second input of the adder 10. The output of adder 10 is the output of the regenerator.

A digital signal (Fig. 2a) from one of the outputs of the control unit 2, as well as a clock signal (Fig. 26) from the output of the controlled delay unit 19, are supplied to the inputs of the EXCLUSIVE OR 11. element. If the positive edges of the clock pulses are in the middle of the information pulses (Fig. 2a, b), at the output of the EXCLUSIVE OR 11 element, the signal has the form shown in FIG. 2c. This signal is averaged in block 12 and fed to the information inputs of the comparators 13 and 20. The average signal level UcR in this case is equal to half the amplitude of the rectangular pulses (Fig. 2c). The threshold voltages U _n and supplied to the threshold inputs of the comparators 13 and 20, respectively, are more and less than the voltage U _Cp (Fig. 2B). o At the same time, on the inverted output of comparator 13 and on the output of comparator 20 there are logical ', the outputs of coincidence unit 14, inverter 15 and coincidence unit 16 are logical 1, 0, and O, respectively, and the states of the reverse counter 17 and the digital-to-analog converter 18 remain unchanged.

If for some reason the clock pulses are shifted to the right (Fig. 2d) from their optimal position (Fig. 26), then at the output of block 14, the duty cycle of the pulses decreases, which leads to an increase in voltage at the output of the averaging block 12 (Fig. 2e) and a change in the states of the outputs of the comparator 13, the coincidence unit 14 of the inverter 15. In this case, the pulses from the output of the generator 21 pass through the coincidence unit 16 to the reversible counter 17, which in this case operates in direct counting mode. The operation mode of the reversible counter 17 is determined by the signal level at the direct output of the comparator · 13. The counting result * of the counter * counter 17 is converted by the digital-to-analog converter 18 into a voltage that reduces the delay of the clock pulses at the output of the controlled delay unit 19.

When the clock pulses are shifted to the left of their optimal position, an increase in the delay is ensured by the operation of the reverse counter 17 in the mode

14241 of the countdown in a similar manner (Fig. 2e, d).

Claims (1)

Claim Regulator of a quasi-digital digital signal according to ed. St. No. 1022316, characterized in that, in order to increase the noise immunity, q by increasing the accuracy of phasing of clock pulses, a series-connected EXCLUSIVE OR element, an averaging unit, a first comparator, a first matching unit, a ι inverter, a second matching unit, a reversible counter, a digital-to-analog converter are introduced and a controlled delay unit, as well as a second comparator and a pulse generator, and the first ± output of the frequency divider is connected to the second input of the output unit through a controlled delay unit, the output of which connected to the first input of the EXCLUSIVE OR element, one of the outputs of the control unit is connected to the second input of the EXCLUSIVE OR element, the output of the averaging unit is connected to the first input of the second comparator, the output of which is connected to the second input of the first coincidence unit, the output of the pulse generator is connected to the second input of the second coincidence unit, the second output of the first comparator is connected to the second input of the reverse counter, and the second inputs of the first and second comparators are connected to the corresponding threshold voltage sources niy.