SU1431047A2 - Sawtooth voltage generator - Google Patents

Abstract

The invention relates to a pulse technique and can be used in television signal conditioners with a solid-state photoelectric converter. The purpose of the invention is the expansion of functionality - achieved by providing adjustment of the duration of sawtooth voltage pulses over the entire operating range of input voltages, as well as by varying the duration of these pulses each separately and ensuring control of the initial voltage in the intervals of pulses. The generator contains an integrator 1 with a control input 2, a source 3 of synchronizing 1; their pulses, a second integrator 4, a bus 5 of a source of reference voltage, a signal bus 6, a comparator 7, an element OR 8, a third integrator 21, an additional comparator 22, an additional the element OR 23, the limiting element 24, the switch 25, the initial voltage bus 26, the control voltage bus 27, the reference voltage bus 30. 4 il. 30 & (L

Description

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The invention relates to a pulse technique and can be used, for example, in television signal conditioners with solid-state photoelectric converters.

The aim of the invention is to expand the functionality by providing adjustment of the duration of sawtooth nag pulses in the entire operating range of input voltages, changing the duration of these pulses separately, ensuring control of the initial voltage in the intervals between pulses.

FIG. 1 shows the structural electrical circuit of the device; in fig. 2 - electric circuit of the rator; in fig. 3 - diagrams for the operation of the device; in fig. 4 shows an example of a technical implementation and a transitional characteristic of a restrictive element.

Sawtooth generator 25 ra 21 is connected to the output element

contains the first integrator 1, the control input 2 of which is connected to the output of the source of the 3 clock pulses, the second integrator 4, the bus

5 sources of reference voltage, signal control input of the switch 25,

The bus 6, the comparator 7 and the OR element 8, the first input of which is connected to the output of the comparator 7, the second input to the output of the source 3 clock pulses, and the output is connected to the control input of the second integrator 4. The control input of the comparator is connected to the output The first integrator 1, the signal input 9 of the first integrator 1 and the reference input 10 of the second integrator 4 are connected to the signal bus 6, and the reference input 11 of the first integrator 1 and the signal input 12 of the second integrator are connected to the bus 5 of the voltage source. The integrator 1 and 4 is made on the operational amplifier 13, the non-inverting input of which is connected to the signal input of the integrator through the first resistor 14, through the second resistor 15 to its reference input, the inverting input is connected to the signal input through the third resistor 16 with the first plate of the capacitor 17, in parallel with which is connected a control key 18, the control input of which is connected to the control input of the integrator, and the second plate

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the capacitor 17 is connected through the resistor 19 to the integrator and through the fifth resistor 20 to the output of the operating amplifier and the output of the integrator.

The device also contains a third integrator 21, an additional comparator 22, an additional element OR 23, a limiting element 24, a switch 25, an initial voltage bus 26, a control voltage bus 27 connected to the reference input of an additional comparator 22, the signal input of which is connected to the output The third integrator 21, the signal input 28 of which is connected to the bus 5 of the voltage source, the reference input 29 to the output of the limiting element 24, the input of which is connected to the signal bus 6, the reference input to the bus 30 op Nogo voltage comparator 7, the third input uscheavl yuschy integratoILI 8 and the first input of the additional OR gate 23, the second input of which is connected to an additional output of the comparator 22, and vpsod - with

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the first input of which is connected to the output of the second integrator 4, the second input is connected to the bus 26 of the initial power, the output, to the output of the device.

Switch 25 can be performed on an axis of the adder with a switched output, the inputs of which are supplied from the bus 26 and from the output of the integrator 4, and the output is switched by the element OR 23.

The device works as follows.

During the time of action of the pulse (Fig. 3A) coming from the source of the 3 synchronizing pulses (Fig. 1), the potentials corresponding to the potentials at the inputs 9 and 12, i.e. corresponding to the level on the signal bus 6 and the bus 5 of the voltage source. The same impulse through the element OR 8, arriving at the control input of the third integrator 21, sets at its output a potential corresponding to the voltage level on the bus 5 of the reference voltage source (Fig. ES). After the termination of the pulse at the moment of Tm, the potentials on

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The outputs of integrator 1, 4 and 21 begin to vary linearly and by the time of arrival the next 1 (its impulses reach the values of inputs 11, 10 and 29, respectively. Fig. 36 shows the character of the change of output potentials from the second 4 and third 21 integrators with change the input voltage on the signal bus 6 for its values that do not exceed the potential of the bus 30 of the reference voltage of the comparator 7. When this potential is exceeded, the comparator 7 is activated, the pulses from the comparator 7 are added to the element 8 with pulses 3 from the source clock and myl-- cos (FIG. Rear, curve 1) and controlling the ON time of the second integrator 4 such that the output of the integrator with a potential at time T is always the same value.

The third integrator 21 (ip 1) produces the same sawtooth voltage pulses as the second integrator 4, up to the moment when the input voltage on the signal bus 6 becomes less than the voltage on the mnlie 30 of the comparator reference voltage 7. At A further reduction of the voltage on the signal bus 6 at the output of the limiting unit 24. (The technical implementation example and transient characteristic of which is shown in Fig. 4a, b) the voltage is equal to the voltage on the bus -30 of the reference voltage of the comparator 7 and the signal type jja c exit third integ Ator 21 remains unchanged (Fig. Sv, curve 1).

The signal from the output of the third integrator 21 (curves 1 in Fig. Zv, e) is compared by an additional comparator 22 with the control voltage supplied to the bus 27 of the control voltage (Kri 2 in Fig. Sv, e).

The resulting comparison pulse from the output of the additional comparator 22 through the second element OR 24 controls the switch 25, which for the duration of this pulse generates at its output the initial voltage () coming through the second input of the switch 25 from the initial voltage bus 26. After the termination of this pulse at the output of the switch 25

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there is no sawtooth voltage, I act from its first entrance, i.e. voltage from the output of the second tag-rator 4 (Fig. 3g, e).

The first 1, second 2 and third 21 integrators are made according to the same functional diagram, bounded in FIG. 2, and the following work ;. in a way.

Q When the voltage is closed; -: an external key 18 during a voltage pulse to its control input, the potential at the integrator's output is kept flat on the input potential at inputs 12 and 9. When the key 18 is opened, the capacitor 17 starts charging direct current through the resistor 16 to the potential of the inputs 10 and 11.

Q This functional block diagram of integrators provides the possibility of forming on its course during the time between two pulses arriving at the control

Claims (1)

5 input, linearly varying voltage in the range from the initial to the final potential at its inputs. Invention Formula n sawtooth generator by author. St. No. 1149390, about tl and -. That in order to extend the functionality by providing the possibility of adjusting the duration of the saw voltage pulses in the entire working range of input voltages, changing the duration of these pulses each individually, providing control of the initial voltage in the pauses between pulses, a third integrator, an additional comparator, an additional OR element, a limiting element, with a commutator, an initial voltage bus, a control voltage bus, are introduced into it. and, connected to the reference input of an additional comparator, the signal input of which is connected to the output of the third integrator, the signal input of which is connected to the bus of the voltage source, the reference input to the output of the limiting element, the input of which is connected to the signal bus, the reference input to the reference bus voltage of the compiler, the control input of the third integrator is connected to the output of the OR element and the first input of the additional element five 0 0 five OR, the second input of which is connected to the output of the additional comparator, and the output to the control input of the switch, the first input of which is the S17 connection G6 P 1b and a l ". Uoh and srig.Z with the output of the second integrator, the second input with the initial voltage bus, the output with the output of the device. one W 20 - / Oftajyf Oi / ffjra t five and you. ofrai. ..J Phil