SU1109861A1 - Frequency synthesizer - Google Patents

Abstract

A FREQUENCY SYNTHESIZER containing N frequency dividers with a variable division factor, the information inputs of each of which are connected to the corresponding outputs of the register of storing and recording information, whose information inputs are the installation inputs of the frequency synthesizer frequency codes, in order to ensure synchronous switching output frequencies without interrupting the phases, the serially connected setup block, the counter, the AND element, the frequency divider, and the fixed frequency divider are introduced into it the dividing effect and the synchronization unit, the output of which is connected to the control input of the information storage and recording register, the second inputs of the counter and element I are combined and are the input of the frequency synthesizer, the setup inputs of each of the N variable frequency dividers with a variable division factor and a fixed unification coefficient (L of the sensor and connected to the output of the initial installation block, and the output of the element I is also connected to the counting input of each of the N frequency dividers with a variable coefficient tom division

Description

(11) The invention relates to radio engineering and can be used in frequency synthesis systems, communication techniques and radio measuring devices. A frequency synthesizer is known that contains series-connected pulse generator, counter, group of elements And frequency dividers. The frequency synthesizer simultaneously generates N output signals The drawback of the synthesizer is the formation of only a grid of fixed frequencies, since each of the N frequency dividers is made with a fixed division factor. The technical entity to be proposed is a frequency synthesizer containing N frequency dividers with a variable division factor, the information inputs of each of which are connected to the corresponding outputs of the storage register and information recording, whose information inputs are the input settings of the frequency synthesizer 21 frequency codes. However, a well-known synthesizer often does not provide synchronous switching of the output frequency grid without a phase break. The purpose of the invention is to provide synchronous switching of the output, often without a phase break. . The goal is achieved by the fact that the frequency synthesizer containing N frequency dividers with a variable division factor, the information inputs of each of which are connected to the corresponding outputs, the information storage and recording registers, the information inputs of which are the settings of the frequency synthesizer output frequency codes , the serially connected setup block, a counter, an AND element, a frequency divider with a fixed division factor and a synchronization block, the output of which is connected to the control unit, are entered The second input of the register of storing and recording information, the second inputs of the counter and the element And are combined and are the input of the frequency synthesizer, the installation inputs of each of the N frequency dividers with variable division factor and the setup input of the frequency divider, j) are divided by the split factor and connected to the output of the block on the initial 2 settings, and the output of the element I is also connected to the counting input of each of the N dividers 14 with a variable division factor. The drawing shows a structural electrical circuit of a frequency synthesizer. The synthesizer contains an installation block 1, a counter 2, an AND 3 element, a divider 4 frequencies with a fixed division factor (DFCD), a synchronization block 5, a register 6 for storing and recording information, dividers 7 for a frequency with a variable division factor (DCD). The synthesizer works as follows. When the power is turned on, the unit 1 of the initial installation automatically generates a pulse at its output for setting the initial zero state of counter 2, DDCD 7 and DFCD 4. When the installation pulse ends, the counter 2 starts counting the sequence of pulses entering the frequency synthesizer input. At the end of the counting, the output of counter 2 forms a logic level 1, which permits the passage through the AND 3 element of the sequence of input pulses to the counting inputs of each of the N DCPD 7 and to the counting input DCDD 4, which synchronously starts counting the input pulses. By the time of the appearance of logic level 1 at the output of counter 2, all transients in the frequency synthesizer must be completed and DPKD 7 and DFCD 4 must be in their initial zero states. These conditions determine the required pulse widths of the Setup and the capacity of counter 2. Each of the N DPCK 7 divides the frequency of the input pulses according to the codes from register 6 recorded in them. The combination of counting cycles determines the corresponding grid of output frequencies, 2.Kv mkt where r for each divider PDKD 7 can be any of a number of numbers 1,2 ,. ..one. The combination of codes at the respective information inputs of the setting of register codes 6 determines the next required grid of output frequencies; A command impulse to set a predetermined grid of frequencies comes from the field unit A of synchronization unit 5, which, when a command signal arrives, will pick up,

one closest pulse from the clock sequence of pulses from the DFCD 4 output; The output pulse from the synchronization unit 5 sets the required combination of codes at the output of register 6 and records the subsequent combination from the inputs of installation of codes for storage in register 6. Combine 1 and codes at the outputs of the register 6 defines a new combination of counting cycles for N PDCD 7 and the corresponding New Output Frequency Grid. The moments of transition to another frequency grid are determined by the occurrence of output pulses at the DFCD output t because each of the frequencies of the output grids is a harmonic of the output frequency of the DFCD 4. Tying these moments to the current time, according to which the command pulse appears carried out by the synchronization unit 5. This ensures synchronous grid switching

output frequencies without discontinuity in phases, since at the end of the last periods of previous frequencies of one grid, strictly exact periods of other frequencies of the next grid begin.

one

l / Wi f ftKii nXi

1- L

The number of different grids is determined in the general case by the minimum grid spacing and the maximum speed of the DCD 7, which determines the choice

highest possible frequency synthesizer frequency.

If the pitch of the frequency grids and the values of the output frequencies are i, -, where I is the sequence number of the frequency,

K is the value of the division factor (, 2,3, ..., 1), then the frequency of the input pulses of the frequency synthesizer f m, where r is the least common multiple of the full set of numerical values K.

The value of n determines the minimum value of the division coefficient of DFCD 4. Using the proposed frequency synthesizer provides synchronous switching of output frequency grids without

phase separation, which allows the synthesis of the -frequencies in a decade way to provide a transition from one different code frequency to another without phase jumps

signal, frequency modulation and manipulation in the output signal without interrupting the phase, and also provides higher spectral characteristics of the output signal.

Claims (1)

A FREQUENCY SYNTHESIZER containing N frequency dividers with a variable division coefficient, the information inputs of each of which are connected to the corresponding outputs of the information storage and recording register, the information inputs of which are the input settings of the output frequency codes of the frequency synthesizer, which differs in that, in order to ensure synchronous switching output frequencies without a break in ₍ phases, series-connected initial installation unit, counter, AND element, frequency divider with a fixed coefficient are introduced into it ntom division and synchronization unit, the output of which is connected to the control input of the register for storing and recording information, the second inputs of the counter and the And element are combined and are the input of the frequency synthesizer, installation> inputs of each of the N frequency dividers with a variable division coefficient and the installation input of the frequency divider with a fixed by a factor are connected and connected to the output of the initial installation unit, and the output of the element f And is also connected to the counting input * of each of the N frequency dividers with a variable dividing factor I. > f 110986