SU1334146A1 - Microprogram control device - Google Patents

Abstract

The microprogram control device relates to the technique of monitoring and diagnosing digital devices and can be used in the development of microprogram computer control devices and microprocessor devices. The purpose of the invention is to expand the functionality of the device by implementing a variable frequency of the formation of micro-instructions. The essence of the invention is that in a known device comprising an address counter 1, a decoder 2, a memory block 10, two groups of elements AND 7, 8, the first element NOT 9, counter 13, the first and second multiplexers II, 12 are additionally introduced , frequency register 14, four triggers 3-6, AND-NO 16 element, the second element NOT 15, two elements OR-NOT 17, 18. 3 Il. (L 27 CO CO 4 05 25

Description

one

The invention relates to computing and can be used in the development of microprogrammed computer control devices.

The purpose of the invention is to expand the functionality of the device by implementing a variable frequency of the formation of micro-instructions.

Figure 1 shows the functional scheme of the device; figure 2 - timing charts of the device; on fig.Z - microinstructions format.

The device contains a counter 1 address, a decoder 2, triggers 3-6, groups 7 and 8 elements AND, element NOT 9, block IO Memory, first 11 and second 12 multiplexers, counter 13, frequency register 14, second element 15, element AND-NOT 16, elements OR-NOT 17 and 18, inputs of clock pulses 19, start 20, information display indications 21, second 22, third 23, first 24 groups of information outputs, output 25 of the address indication of the next micro-command and output 26 of the display the frequency of the device microinstructions.

The device works as follows.

In the memory block 10, in the device preparation mode, a device control program is written preliminarily. This is also a memory block of the permanent memory ROM with a predetermined program according to the time diagrams (Fig. 2). When a high level signal arrives at input 20 of a device, trigger 3 is set to a high signal by a clock signal from the output of multiplexer 11; as a result, triggers 4, 5 and 6 work the conveyor chain to parse the micro-command by clocking signals from the output of a multiplexer 12. At the outputs Triggers 3 - 6 according to the timing diagrams (FIG. 2) are generated by the control signals of the VC memory block, LH decoder, address register +1, and the sync signal Reset the executed microcommand parsing cycle.

The device implements the principle of analysis of microinstructions under the action of a clock signal with a double strobe frequency; their signals.

The signal with a frequency F is fed to the input of the counter 13 and the input of the first multi

34I462

of the type II multiplexer. At the outputs of the counter 13, the sync signals F / 2, F / 4, F / 8 ... are formed. The multiplexers 11 and 12 are wired in such a way that the corresponding inputs of the multiplexer 11 are twice as low as at the multiplexer 12. Thus, for any frequency code, the same information code is present at the outputs of the frequency register 14 at the control inputs of the multiplexer, and at the output of the multiplexers, as shown in FIG. 2, the frequency of the synchronization signal 15 is different by 2 times. On the leading edge of the blue signal: the trigger signal 3 is set to 1. From the inverse output of this trigger, the chip sample signal goes to the IO block of memory 20 | gi. The appearance at the output of trigger 3 of a high level signal and after a quarter of a period the arrival of a clock signal to the clock inputs of flip-flops 4 and 5 generate control signals 25 Lenin decoder 2 LH and add +1 to the address counter 1. After a quarter of the period the clock input of trigger 6 comes the positive edge of the sync signal, which, when the LH signal is on, sets the inverse output of the trigger to 1 and after a quarter of the period with the arrival of the positive signal edge, the signal is generated at the output of the NAND 6 element

2g reset triggers 3, 4 and 6.

The format of microinstructions of the device is shown in FIG.

Each word of memory block 10 has the format shown in FIG. 3. First

40 two high-order bits define format 0 commands. This format is characterized by maximum speed and implements the following microcommands: writing the memory field to the address counter, writing the memory field 1 to the frequency register, loading all the data bits from the memory block ( excluding the second group of information outputs of the memory block), the formation of a sign

5Q format 1 or 2 devices. When nali-. In the fourth output of the decoder 2 of the I or 2 format feature, the third information output of the memory block 10 on the WL-NOT elements is analyzed.

55 17 and 18. The zero value of this signal corresponds to the commands of the format 1 device, the one - to the commands of the format 2 device. Commands are executed and encoded in each format.

313

unary and have their own non-intersection field of operands, which allows their parallel combination in the cycle of one micro-command ..

Claims (1)

Invention Formula A firmware control device containing an address counter, a decoder, a memory unit, two groups of AND elements, a NOT element, the output of the address of the microcommand of the memory block is connected to the information input of the address counter and the output of the address indication of the microcommand of the device These are connected to the first group of informational outputs of the device, characterized in that, in order to spread the application area by implementing a variable frequency of the formation of microcommands, a counter is inserted into it, two iplexer, frequency register, four flip-flops, element AND-NOT, element Н-Е, two elements OR — NOT, the device’s clock input is connected to the counting counter input and to the first information input of the first multiplexer, the information inputs from the second to the Mth connected respectively to the outputs from the first to (M-1) -th counter (where M is the number of microcommand execution frequency values), and connected to the information inputs from the first to (M-1) -th second multiplexer, the control inputs of the first and second multiplexers by They are connected to the output of the frequency register, the output of the first multiplexer is connected to the synchronous inputs of the first and second triggers, the first input of the NAND element and, through the first element, NOT to the sync-to-third signal of the third trigger, the inverse output of which is connected to the second trigger and to the second input of the element, and NOT, the output of which is connected to the inputs of the installation in 46 About the first, third and quarter trigger, the direct output of which is connected to the information inputs of the first and second triggers, the output of the second trigger is connected to the counting input of the address counter, the recording input and output of which are connected respectively to the first output of the decoder and to the address input of the memory block whose sample input is connected to the inverse output of the fourth trigger, whose information input is connected to the device start input and connected to the memory read / write input of the memory block, the first output of the type of microcommand which It is connected to the information input of the decoder, the gate input of which is connected to the inverse output of the first trigger and connected to the information input of the third trigger; the output of the code of execution of the microcommands of the memory block and the output of the indication of the frequency of the execution of the microcommands of the device; the third output of the decoder is connected to the output of the indicator As the device provides information, the fourth output of the decoder is connected to the first inputs of the first and second elements SH-NOT, the outputs of which are connected to the first inputs of the And elements of the first and second groups, the outputs of which are connected respectively to the second and third groups of information outputs of the device, the second output type the microcommands of the memory block are connected to the second input of the first element OR NOT and through the second element NOT to the second input of the second element OR NOT, the outputs of the microoperations floor of the memory block are connected to V eye inputs of AND gates of the first and second groups. Vsh, 1Pshch8gera6 --i ResetI field Format field fPua. 3 Editor E. Kopcha Compiled by M.Silin Tehred I.Popovich Order 3963/45 Circulation 672 Subscription VINILI State Committee of the USSR for inventions and discoveries PZYUZ, Moscow, Zh-35, Raushsk nab., d.4 / 5 Production and printing company, Uzhgorod, st. Project, 4 (Rie. 2 Informative Lod flojieK Proofreader A.Zimokosov