SU1238080A1

SU1238080A1 - Signature analyzer

Info

Publication number: SU1238080A1
Application number: SU833613108A
Authority: SU
Inventors: Леонид Борисович Спирин; Михаил Сергеевич Литвинов; Виктор Евгеньевич Ашурков
Original assignee: Специальное Конструкторское Бюро Института Математики И Механики Ан Азсср
Priority date: 1983-04-11
Filing date: 1983-04-11
Publication date: 1986-06-15

Abstract

Изобретение относитс к области вычислительной техники и может быть использовано дл контрол .дискретных объектов. Целью изобретени вл етс повьшшние достоверности контрол . Отличительной особенностью предложенного сигнатурного анализатора вл етс совмещение функций получени сигнатуры провер емой информации и контрол самого сигнатурного анализатора. При этом контроль анализатора осуществл етс методом подачи тестовой последовательности с выходов младшего разр да счетчика на определенном tipe- менном интервале, который задаетс старшим разр дом счетчика. Поставленна цель достигаетс за счет введени триггера и двух элементов ИЛИ. 1 ил. .The invention relates to the field of computing and can be used to control discrete objects. The aim of the invention is the higher reliability of the control. A distinctive feature of the proposed signature analyzer is the combination of functions for obtaining the signature of the information being checked and controlling the signature analyzer itself. At the same time, the analyzer is monitored by applying the test sequence from the low-discharge outputs of the counter to a certain tipe interval, which is specified by the high-resolution counter. The goal is achieved by introducing a trigger and two OR elements. 1 il. .

Description

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Изобретение относитс к алтоматг-т- ке и вычислительной технике и может быть использовано дл контрольных дискретных объектов.The invention relates to automated technology and computing and can be used for control discrete objects.

Целью изобретени вл етс повыше- 5 ние достоверности контрол .The aim of the invention is to increase the reliability of the control.

На чертеже показана блок-схема устройства.The drawing shows a block diagram of the device.

Устройство содержит триггер 1, элемент ИЛИ 2, счетчик 3, элемент ИЛИ 4, информацирнный вход 5 сигнатурного анализа- гора, формирователь 6 сигнатур,синХровход 7 сигнатурного а1 алнзатора., взеод .8 управлени режимом сигнатурного сигнализатора, вход 9 задани окна измерени сигнатурного анализатора, формирователь 10 импульсов , блок 11 индикации.The device contains a trigger 1, an element OR 2, a counter 3, an element OR 4, an information input 5 of the signature analyzer - a mountain, a driver of 6 signatures, a synchronous input 7 of the signature a1 alnzator. , shaper 10 pulses, display unit 11.

Сигнатурный анализатор работает следующим образом.Signature analyzer works as follows.

В режиме сигнатурного анализа входной информации цифрова последовательность поступает на информационный вход анализатора и через элемент ИЛИ 4 на вход формировател 6 сигнатур в такт с синхросигналами на син- хровходе 7 сигнатурного анализатора.In the signature analysis mode of the input information, the digital sequence is fed to the information input of the analyzer and through the element OR 4 to the input of the generator of 6 signatures per clock with the sync signals on the synchronous input 7 of the signature analyzer.

Эти сигналы синхронизированы с внешними сигналами Старт/стоп на Входе 9 сигнатурного анализатора и формируют с помощью элемента ИЛИ 2 и формировател 10 импульсов соответствующее , измерительное окно. При этом сигнал контрол на входе 8 отсутствует и триггер 1 установлен в такое состо ние, при котором сигнал с его выхода удерживает счетчик 3 в нулевом состо нии.These signals are synchronized with external Start / Stop signals at the Input 9 of the signature analyzer and form the corresponding measuring window using the element OR 2 and the driver 10 pulses. In this case, the control signal at input 8 is absent and the trigger 1 is set to the state in which the signal from its output keeps counter 3 in the zero state.

В режиме контрол анализатора на вход 8 подаетс сигнал контрол (при- . чем на управл ющий вход 9 и информационный вход 5 в этом режиме сигналы не подаютс , т.е. подаетс О). Сигнал контрол синхронизирован с синливаетс In the analyzer control mode, the control signal is input to input 8 (more than control input 9 and information input 5, in this mode, no signals are sent, i.e., O). The control signal is synchronized with sync.

11 1 ТГ11 1 TG

. Пройд элемент ШШ А, 1 поступает на вход формировател 6 сигнатур.. Passing the element ШШ А, 1 is fed to the input of the former 6 signatures.

Задним фронтом синхросигнала 1 воспринимаетс формирователем 6 сигнатур , выходы которого подаютс на блок 11 индикации. Следующий передний фронт синхросигнала возвращает первый разр д счетчика 3 в Исходное состо ние, и на выходе его младшего разр да устанавливаетс О, который, пройд через логический элемент И.ПИ 4, воспринимаетс формирователем 6 сигнатур по заднему фронту второго синхросигнала .The falling edge of the clock signal 1 is sensed by the signature generator 6, the outputs of which are fed to the display unit 11. The next leading edge of the sync signal returns the first bit of the counter 3 to the Home state, and at the output of its low-order bit O is set, which, having passed through the logic element I.PI 4, is sensed by the signature generator 6 on the trailing edge of the second sync signal.

Следовательно, на выходе младшего разр да счетчика 3 формируетс последовательность единичных и нулевых уровней, котора поступает на вход 20 формировател 6 сигнатур. Эта последовательность формируетс до тех пор, пока на выходе старшего разр да счетчика 3 не по витс сигнал 1, который передним фронтом устанавливает триггер t в исходное состо ние, а на входе элемента ИЛИ 2 имитирует сигнал Стоп, который поступает на вход формировател 10 импульсов и прекращает формирование временного интервала .Consequently, at the output of the least significant bit of the counter 3, a sequence of single and zero levels is formed, which is fed to the input 20 of the generator of 6 signatures. This sequence is formed until the output of the most significant bit of counter 3 is not received by signal 1, which sets the trigger t to the initial state by the leading edge, and at the input of the element OR 2 imitates the stop signal, which is fed to the input of the imager 10 pulses and stops the formation of a time interval.

Таким образом, на входе формировател 6 сигнатур в режиме контрол в.сегда формируетс определенна последовательность за определенный ин- JJ тервал времени и преобразуетс всегда в определенное состо ние.Thus, at the input of the signature generator 6 in the control mode, a certain sequence is formed at all times for a certain time interval and is always transformed into a certain state.

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Claims

Invention Formula

40

A signature analyzer containing a signature driver, a display unit, a pulse driver, and a counter, the output of the pulse driver being connected to the control inputs on the syncro. HOUSE shaper signatures, group input 7 signature analyzer. whose outputs are connected to a group

the indication block inputs, the signature generator synchro rotor is a sync trigger of the signature analyzer, characterized in that, in order to increase the reliability of the counter, the front edge of the control signal switches trigger 1, which removes the zero signal from counter 3, and also simulates the input of the OR 2 element the start signal, which is fed to the input of the driver 10 pulses and starts ei o. I

The clock signal with the leading edge, which coincides with the leading edge of the control signal, flips the first (lower) bit of counter 3 and, at its output, low bit of the set 50

55

l, a trigger and two OR elements are entered into the signature analyzer, and the input of the measurement window of the signature analyzer is connected to the first input of the first OR element, the second input of which is connected to the single trigger input and is the control input of the signature analysis mode

pouring

11 1 TG

. Passing the element ШШ А, 1 is fed to the input of the former 6 signatures.

The falling edge of the clock signal 1 is sensed by the signature generator 6, the outputs of which are fed to the display unit 11. The next leading edge of the sync signal returns the first bit of the counter 3 to the Home state, and at the output of its low-order bit O is set, which, having passed through the logic element I.PI 4, is sensed by the signature generator 6 on the trailing edge of the second sync signal.

Therefore, at the output of the lower bit of the counter 3, a sequence of single and zero levels is formed, which is fed to the input of the generator of 6 signatures. This sequence is formed until then. while at the output of the high bit of counter 3, signal 1 does not appear, which by the leading edge sets the trigger t to the initial state, and at the input of the element OR 2 imitates the stop signal, which enters the input of the pulse former 10 and stops the formation of the time interval.

Thus, at the input of the signature maker 6 in the control mode, a certain sequence is always formed in a certain time interval and is always transformed to a certain state.

Invention Formula

55

l, a trigger and two OR elements are entered into the signature analyzer, and the input of the measurement window of the signature analyzer is connected to the first input of the first OR element, the second input of which is connected to the single trigger input and is the control input of the signature analyzer mode, the output of the first OR element is connected to the input of the pulse former, the information input of the signature analyzer is connected to the first input of the second OR element, the output of which is connected to the information input of the signature generator, sync course of the signature analyzer

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Editor M. Tsitkina

Compiled by N, Toropova

Tehred L. Serdyukova Proofreader L. Pilipenko

Order 3293/50 Circulation 671 Subscription

VNIIPI USSR State Committee

for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5

Production and printing company, Uzhgorod, st. Project, 4

12380804

connected to the counter input of the counter, the overflow of which is connected to the zero input of the trigger and to the third input of the first OR element, output 5 of the trigger is connected to the counter enable input of the counter, the low-end output of which is connected to the second input of the second OR element.