SU1310870A1 - Multichannel telemetering system - Google Patents

Abstract

The invention relates to a technique for transmitting information and can be used in those areas of technology where redundancy is required, especially in the case of small a priori information and limited time for its transmission. The purpose of the invention is to increase the information content by increasing the compression ratio. , af lleg foutaf focmt tSroff Receive i / t g Multichannel telemetric system contains on the transmitting part synchronizer 1, 2 channel switch, analog-to-digital converter 3, information redundancy reduction unit 4, buffer storage unit 5, element MB, channel address encoding unit 7, delay element 8, and at the receiving part - block 9-allocation of the frame marker, first, second and third elements AND 10, 11, 12, chronizer 13, buffer storage unit 14, digital-to-analog converter 15, switch 16 channels, OR element 17, register 18 code and addresses. In a multichannel telemetric system, a group frame is formed at the transmitting part and transmitted to the communication channel; at the receiving part - the introduction of the beginning of the frame, the reception of the frame and the distribution of data on the respective consumers. 2 Il. W W with 00 # «1. /

Description

The invention relates to a technology for transmitting information and can be used in those areas of technology where redundancy is required, especially in the case of small a priori information and limited time to transmit it, for example, to communicate with spacecraft, in an emergency situation of telemetry objects and t .d

The chain of the invention is to increase the information content by increasing the compression ratio.

Figure 1 shows the functional diagram of the multichannel telemetering system; figure 2 - the structure of the telemetry frame.

The multichannel telemetering system contains a transmitter part consisting of synchronizer 1, switch 2 channels, analog-digital converter 3, information redundancy reduction unit 4, buffer storage unit 5, element 6, block 7 of encoding the address of channels, element 8 delay, the receiving part, consisting of block 9, the allocation of the frame marker, the first, second and third elements 10–12, the chronizer 13, the buffer storage unit 14, the digital-to-analog converter (D / A converter) 15, the switch 16 channels, the OR element 17, register 18 address code.

The operation of the multichannel telemetering system is as follows.

The synchronizer 1 signals control the operation of the 2 channel switch with

by means of which the input of the analog-digital-40 code of addresses to its output

The transducer 3 receives signals from all N channels. Unit 3, in accordance with the amplitude of the input signal Si, generates a binary code combination, which is sent to the address code register 18, and is sent to the information redundancy block 4. In this block, significant samples are taken in accordance with the algorithm In the form of information code combinations, they are sent to the buffer storage unit 5. The signal of a significant sample from the output of the redundancy redundancy block 4 of the information source opens the AND 6 logic element on the control input and the channel frequency pulse with t synchronous output 1 is fed to the information

the input to the channel address encoding unit 7, which is an N-bit shift register. Thus, in the lower order of block 7, symbol 1 is fixed corresponding to this channel. The same channel frequency pulse, passing through delay element 8, produces a shift in block 7 content, freeing the least significant bit to receive the O or 1 symbol of the next channel. After the arrival of N channel pulses in block 7, the full positional code of the channel address is recorded, which is read into the buffer storage unit 5 with a pulse of the sampling frequency of 5, the functions of which include the transmission of messages into the communication line at a uniform speed. On the receiving side, a full telemetry signal is simultaneously received at block 9 of the frame marker and information inputs of logic i elements 12 and 10. In block 9, operating, for example, according to the pulse selector principle, a frame marker signal is extracted from the full telemetry frame which enters the chroniser 13 and synchronizes its work. With the arrival of each signal of the frame marker, the chronizer 13 generates at its third output a gating pulse with a duration equal to the duration of the generalized positional code of the channel addresses. A gating pulse simultaneously arrives at the control inputs of logic gates And 12, 10, and 11. At the same time, the And 12 turns out to be locked and position symbols

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the elements arrive, and elements 10 and 11, on the contrary, are open. As a result, the characters of the positional code of the addresses through the AND 10 element are the incoming pulses from the second output of the chronizer 13 through the elements 11 and OR 17 arrive at the shift input of the register 18, causing promotion

50 characters of the address code at the end of the register. After the writing of the address code to the register 18 at the gate third output of the chroniser 13 is completed, the control pulse 55 stops, the I element opens to the control input and at this point the channel information words entering the receiving part in the telemetry frame are fed to the I 12 element receiving block 14 of the buffer memory. Their entry into this block occurs under the influence of clock pulses from the second output of the chroniser 13 to the shift input. At the same time, elements And 10 and 11 are closed by control inputs. Due to this, the false recording of information words through the AND 10 element into the register 18 is closed, and the false pushing of the address code bits from the register 18 by clock pulses over the AND 11 and OR 17 elements is excluded. From this moment the shift of the generalized position code of the addresses written in the register 18, channel pulses are produced, from the chronizer 13, coming through the OR element 17. In the shift shift, the signals of the address code bits are sequentially pushed out of the register 18 and fed to the read input of the buffer memory About block 14. If the corresponding bit of the generalized position code of addresses is 1 (this means that the information code of this channel is in the telemetry frame) and it is pushed out of register 18, then the receiving block 14 receives an impulse to match It does not affect which information code of the corresponding channel enters the DAC 15 and, in the form of an analog signal, switches the 16 channel to the required channel. The reset of the D / A converter 15 and switching of channels in the switch of 16 channels is also performed by channel pulses from the first output of the clock 13, but leading read pulses by the delay time in the OR element 17 and in the register 18. In the case of ejection from the register 18, the corresponding channel which does not carry the information code in the frame, the read pulse in block 14 is not detected.

The DAC 15 and the switch are 16 channels in this 50 units of the channel address encoding unit.

case under the influence of the channel pulse from the chronizer 13 triggered idle. In this way, the compressed telemetry frame is received and stretched, which allows cyclic switching to unambiguously distribute analog information to the corresponding channels.

on the receiving part - the channel switch, the address code register, the frame marker selection block and the first, second and third elements AND and OR, the information inputs of the first and third elements AND, and the input of the frame marker selection block are connected and connected to the input part of the mouth

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A multichannel telemetering system containing a synchronizer, an analog-digital converter and a buffer storage unit on the transmitting part, a synchronizer on the receiving part, the first and second outputs of which are connected to the control input of the digital-to-analog converter and the shift input of the buffer storage unit, respectively, the outputs of the buffer memory block are connected to the inputs of a digital-to-analog converter, characterized in that, in order to

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Informability by increasing the compression ratio, a channel switch, an information redundancy reduction block, a channel address coding block, a delay element and an AND element, channel switch information inputs are input-1 and a transmission part of the device, switch output are added to the transmitting part. channels through an analog-to-digital converter connected to the first input of the redundancy reduction block, the first output of which is connected to the first input of the buffer storage block, the output of which is you. the second part is connected to the output of the channel address coding block, the first synchronizer output is connected to the control input of the channel switch and the installation input of the channel address coding block whose input is shifted to the delay element, the second synchronizer output is connected to the second to the input of the block. redundancy of information, the second output of which is connected to the control input of the element And, the third output of the synchronizer is connected to the input of the delay element and to the information input element And, the output of which is connected to the information input 35

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on the receiving part - the channel switch, the address code register, the frame marker allocation unit and the first, second and third elements AND and OR, the information inputs of the first and third elements AND, and the input of the frame marker allocation unit are connected and connected to the input part of the device5 13

The first output of the synchronizer is connected to the first input of the OR element and to the control input of the channel switch, respectively, the second output of the synchronizer is connected to the information input of the second AND element, the output of which is connected to the second input of the OR element, the third output of the synchronizer is connected to the control inputs of the first, the second and third elements And, the output of the element OR is connected to the -shift input registMar e ffoffpct

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The address code code, the information input of which is connected to the output of the first element I, the output of the third element I is connected to the information input of the buffer storage unit, the read input of which is connected to the output of the address code register, the output of the D / A converter is connected to the information input

The channel switch JO, the outputs of which are the outputs of the receiving part of the device.

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Rig. 2

Editor M. Tsitkina

Compiled by I.Kuznetsov

Tehred M. Khodanich Proofreader N. Povidaychik

Order 1896/48 Circulation 544 Subscription

VNISH1I USSR State Committee

for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5

Production and printing company, Uzhgorod, Projecto st., 4

Claims (1)

Claim A multichannel television measuring system containing a synchronizer, an analog-to-digital converter and a buffer memory on the transmitting part, a chronizer on the receiving part, the first and second outputs of which are connected to the control input of the digital-to-analog converter and to the shift input of the buffer memory, respectively, the outputs of the buffer memory are connected to the inputs of the digital-to-analog converter, characterized in that, in order to increase information content by increasing the compression ratio, n and the transmitting part additionally includes a channel switch, an information redundancy reduction unit, a channel address encoding unit, a delay element and an I element, the channel switch information inputs are inputs of the transmitting part of the device, the channel switch output is connected via an analog-to-digital converter to the first input of the information redundancy reduction unit , the first output of which is connected to the first input of the buffer storage unit, the output of which is the output of the transmitting part, and its second input is sub It is connected to the output of the channel address encoding block, the first output of the lot signal using the 16 channel switch is sent to the desired channel. Setting the DAC 15 to its initial state and switching channels in the 16 channel switch of the out-synchronizer is connected to the control input of the channel switch and to the installation input of the channel address encoding unit, the input `` Shift '' to which · 40 is also connected to the output of the element by channel pulses from the first output of the chronizer 13, but ahead of the read pulses by the delay time in the OR element 17 and in the register 18. If 45 is ejected from the register 18, the zero corresponds to the channel that does not carry the information code in the frame, the pulse with reading in block 14 is not issued. The DAC 15 and the switch 16 channels in this 50 case under the influence of the channel impulse from the chronizer 13 are idled. Thus, the reception and stretching of a compressed telemetric frame occurs, which allows 55 to unambiguously distribute analog information through the corresponding channels through cyclic switching. delays, the second output of the synchronizer is connected to the second input of the block. Reducing information redundancy, the second output of which is connected to the control input of the And element, the third output of the synchronizer is connected to the input of the delay element and to the information input of the And element, the output of which is connected to the information input of the channel address encoding block , on the receiving part - a channel switch, an address code register, a frame marker allocation unit and the first, second and third AND and OR elements, information inputs of the first and third AND elements and the input of the marker block selection frame are combined and connected to the input of the receiving part of the mouth 5 ί: The first synchronizer output is connected to the first input of the OR element and to the control input of the channel switch, respectively, the second synchronizer output is connected to the information input of the second AND element, the output of which is connected to the second input of the OR element, the third synchronizer output is connected to the control inputs of the first, second, and of the third AND element, the output of the OR element is connected to the shift input register 10,870 6 / address code, the information input of which is connected to the output of the first AND element, the output of the third AND element is connected to the information input $ of the buffer storage unit, the read input of which is connected to the output of the address code register, the output of the digital-to-analog converter is connected to the information input 10 of the channel switch, outputs which are the outputs of the receiving part of the device.