SU1304175A1 - Binary code-to-binary-coded decimal code converter - Google Patents

Abstract

The invention relates to the field of automation and computer technology and can be used in the construction of computing and measuring devices. The purpose of the invention is to simplify the converter. This goal is achieved by the fact that the combinational converter contains a group of summing-up rulers, each of which includes a group of multiple-input adders and a group of correction blocks, the correction blocks being performed on 5-bit binary-to-binary converters, 1 or less. 00 about SP

Description

The invention relates to automation and computing and can be used to build converters for computing and measuring devices.

The purpose of the invention is to simplify the converter.

The drawing shows the block diagram of the proposed 24-bit binary code converter

The Converter contains summing Rus 1 and 2, each of which consists of adders 3 and blocks 4 correction

The first rus contains-decades, each of which includes a 4-bit multi-input adder, the outputs of which are connected to the corresponding inputs of the binary-to-binary converter in this decade 1-2-4-8. The input voltage of such converters is equal to 6. The lowest bit does not change. The junctions of the lower 14-bit inputs of the binary code are connected to the inputs of the adders of each decade of the first stage. Branches are made in accordance with the weights of binary bits.

To convert the bits from the 14th to the 23rd input binary code, the second conversion version is used. It consists of 4 decades, each of which also includes a 4-bit multi-input adder, the outputs of which are connected to the corresponding inputs of the code converters of this decade. The inputs of the adder are connected to the branches of the discharge inputs and outputs of the code converters corresponding to the decades of the first rus. Thus, by distributing the bit inputs, the weight of each binary bit is converted into a binary-decimal code, and the branches are grouped by decade. code converter of this decade. The higher bits of the code converter are of weight 10 and are transferred to the next adder, Mlad10

15

20

used code converters in each decade.

The construction of multi-input adders is performed on the basis of 2- and 4-bit adders. This uses the following correspondence between the input and output bits of the adders:

35.4., 3S, + 2S, - for a 2-bit adder;

S, + S, j + S, + S4 + S 5 - for a 4-bit adder,

where s; 2

Then, for example, for the second decade, converters totalizers are entered as follows:

7S, +

5S, j MS, +284 +38 + 683 + 28

S, + 282 + 7834-284

n

8, + 28 +38 + 284 + 85J2

25 S, + 28, + 8, + 8 + 285-i 8, + 8, + 8 + 84 + 85 + 8.

In each of the three decades, it is permissible to replace a pair of 2-bit adders by one 4-bit. In this scheme

30 of the proposed converter contains the same number of integrated circuits as the scheme of the known, however, instead of integrated circuits, code converters use simpler

eg and cheap integrated circuits of 2-bit adders.

Claims (1)

Invention Formula Q Binary Code Converter binary-decimal containing group-. pu ordered by seniority summing rus of increasing bitness, each of which contains iT 45 group of adders and a group of correction blocks, whose inputs are connected to the outputs of all bits, except the younger ones, of the corresponding adders, the discharge outputs of the correction blocks are connected 50 with the inputs of the corresponding bits of the adder of the next older rus, and the transfer outputs of the correction blocks, except for the last one, in each summing rus are connected to the inputs of the corresponding bits 1-2–4–8 of the next 55 code given, decades. The second rus of the adder of the same russ, the outputs will perform the conversion 10 of the transfer of the higher correction block, the higher bits of the binary code for each but the last, summing up the limited bit size of the rus connected to the inputs used code converters in each decade. The construction of multi-input adders is performed on the basis of 2- and 4-bit adders. This uses the following correspondence between the input and output bits of the adders: 35.4., 3S, + 2S, - for a 2-bit adder; S, + S, j + S, + S4 + S 5 - for a 4-bit adder, where s; 2 Then, for example, for the second decade, converters totalizers are entered as follows: 7S, + 5S, j MS, +284 +38 + 683 + 28 S, + 282 + 7834-284 n 8, + 28 +38 + 284 + 85J2 25 S, + 28, + 8, + 8 + 285-i 8, + 8, + 8 + 84 + 85 + 8 In each of the three decades, it is permissible to replace a pair of 2-bit adders by one 4-bit. In this scheme 30 of the proposed converter contains the same number of integrated circuits as the scheme of the known, however, instead of integrated circuits, code converters use simpler eg and cheap integrated circuits of 2-bit adders. Invention Formula Q Binary Code Converter binary-decimal containing group-. pu ordered by seniority summing rus of increasing bitness, each of which contains iT 45 group of adders and a group of correction blocks, whose inputs are connected to the outputs of all bits, except the younger ones, of the corresponding adders, the discharge outputs of the correction blocks are connected 50 with the inputs of the corresponding bits of the adder of the next older rus, and the transfer outputs of the correction blocks, except for the last one, each summed 313041 the corresponding bits of the neighboring higher adder of the neighboring older rus, the bit outputs of the corr. the older russian responses are the outputs of the three most significant bits of the corresponding decade of the converter, the outputs of the lower bits of the adders of the higher rus are the outputs of the lower bits of the corresponding decades of the converter, whose inputs are connected fo to the inputs of the adders according to the weights of the corresponding binary bits younger bit yes sum754 In addition to the older one, each rus is connected to the low-order input of the corresponding adder of the next highest rus; the low-end input of the converter is the output of the low-order converter, which differs from input, and the correction blocks are made in the form of five-bit binary-to-binary converters. Editor M.Tovtin Compiled by N. Shelobanova Tehred and. Popovich Order 1324/57 Circulation 902 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab, 4/5 Production and printing company, Uzhgorod, Projecto st., 4 Proofreader E.Roshko