SU1681303A1 - Divider - Google Patents

Abstract

The invention relates to computing and can be used in general-purpose and specialized computers for building devices for dividing numbers. The aim of the invention is to increase speed. The device contains a group of computational nodes 1i-1m, a group of nodes 2i-2m of generating functions of transfer generation and transit, a group of nodes of transfer formation to the highest bit, a group of nodes 4i-4m of forming a private digit. 5 il.

Description

The invention relates to computing and can be applied in high-speed arithmetic devices for performing the operation of dividing numbers.

The aim of the invention is to improve the speed of the device.

Figure 1 shows a block diagram of a device for dividing; figure 2 - structural diagram of one of the options for implementing the device; figure 3-5 is a functional diagram of the cells used in the structure in figure 2.

The device for dividing contains (fig. Computational nodes 1i-1m, nodes 21-2t forming transfer generation and transit functions, nodes 3i-3m transferring to high order, nodes 4t forming private numbers, divider input 5-7, divisible and logical inputs 6-7 zero, output 8 private, first 9 and second 10 residual outputs, input 11 logical units, correction input 12, correction output 13, outputs 14i-14m with sum of 15i-15m transfers of computation nodes 1i-1m, respectively, first 16i-16m and second 17i -17m outputs of nodes 2i-2m, respectively, outputs 18i-18m of nodes 3i-3m, inputs 19i 19m of nodes 4i-4m and inputs 20i-20m settings.

One of the possible implementations of the device for dividing in the form of a modified iterative network for a 4-bit divider and an 8-bit divisible is shown in FIG. The network uses 21-23 cells of three types.

The cell 21 of the first type contains (FIG. 3) the element EXCLUSIVE OR 24, the one-bit binary adder 25, the element AND 26, the element OR 27, the input 28 of the digit of the divider, the input 29 of the control signal for a given row of the matrix (bit private formed in the previous matrix matrix), input 30 sum and transfer input 31 from the previous matrix row, input 32 transfer from the next least significant bit of the given matrix row, output 33 sum and output 34 of the transfer of this cell, output 35 of the generation function G and the output 36 of the transit function T of transfer, formed in this cell.

Cell 22 of the second type contains (FIG. 4) a one-bit binary adder 37, element AND 38, element OR 39, control signal input 40 for a given array row (bit private, formed in the pre (L

WITH

about

00

with about

SA)

The previous row of the matrix), the input 41 sums and the input 42 of the transfer from the previous row of the matrix, the input 43 of the transfer from the next least significant bit of the given row of the matrix, the output 44 of the transfer of the given cell, the output 45 of the generation function G and the output 46 of the transit function T of transfer formed in this cell.

The third type cell 23 contains (FIG. 5) an element NOT 47, elements AND 48-56, elements OR 57-59, correction input 60 (transfer output to the high-order bit of the previous matrix row), transfer input 61 from the high order of the given matrix row, inputs 62-66 of the transfer generation function Gi-Gs from the outputs of cell 22 and cells 21 from the first to the fourth of this matrix row, respectively, inputs 67-70 of the transfer transit functions Ti-T4 from the outputs of cell 22 and cells 21 from the first on the third of a given row of the matrix, respectively, the output of 71 bits of the private and the output of 72 transfers to the highest digit of the given row of yes Atritsa.

Each of the nodes 1i-1m is designed to calculate the corresponding balance in the form of two numbers: the first number made up of bitwise sums, and the second number made up of bitwise transfers (the sum of these two numbers is equal to the corresponding balance). The input information for each of the nodes 1 are three numbers: the first is the divisor, the second and the third are a set of bit sums and bit-wise transfers of the corresponding residue (for the first calculator, the second number is the dividend, and the third number is zero information) the younger bits coming from the first 6 and second 7 inputs of the divisible device, in fact, in each node, the value of the remainder, presented as a set of bits of bits, is added to the value of the divider in n IOM or additional code (i.e., a divisor is added or subtracted) in accordance with an algorithm without the reduction of the residue, thereby forming a projectile loader code dvuhr next residue. The peculiarity of the first node 1i is that either the values of the dividend and zero information are supplied to its inputs of the second and third groups, respectively, or (with repeated use of the device) the value of the remainder of the first 9 and second 10 outputs of the remainder of the device as a set of partial sums and bitwise transfers.

One of the possible implementations of nodes 1i-1m is their construction in the form of a set of elements EXCLUSIVE OR

24 and adders 25 and 37 (fig.Z and 4), between which there are no transfers.

The nodes 2i-2m for each bit determine the values of the functions of the generation of Gn and of the transit of the transfer of Tp by the values of m of the bit sum Sn and the transfer of In arriving at this bit, while

Gn sn lrii

tp sn + in;

l 1,2N,

where N is the number of digits of the divider, taking into account the sign bit (in the example of figure 2, N 5).

According to the value of the transfer to the senior section of the previous row of a number K | arriving at the input 60 of cell 23, and the value of transfer from the first bit of the given row lo received at the input 61 of cell 23, additional functions of generation Go and transit transit To: That To Ki + lo.

Nodes 2i-2m can be implemented on the elements And 26, 38, 48, elements OR 27, 39, 57 and the element NOT 47 (Fig.3-5).

Nodes 3) and 4 | the values of the functions of generation and transfer of transit generated by the nodes 2i, calculate the value of K | the transfer to the highest bit of a given row of the matrix and the value of the qi bit of a quotient, respectively. In this case, the functions implemented by nodes 3i and 4 | are defined by expressions.

Ki Gi + T2Sz + Ta-Tz-Gn + ... + Ta-Tz-Ty-g GN;

qt Go + ToGt + ToTiG2 + ... + TO-TI ... TN-I

GN.

For the case of implementing the device for dividing, shown in Fig. 2, nodes 3i and 4 | are determined by the expressions (figure 5):

K | G2 + T2-G3 + T2-T3-G4 + T2-T3-T4-G5;

qi Go + To-Gi + To G2 Ti + ToT gTz-Sz +

4TO Tl-T2.T3 G4 + To-TlT2-T3-T4-G5

Nodes can be implemented on the elements And 54-56 and the element OR 59, and formers 4i-4m - on the elements And 49-53 and the element OR 58.

Consider the operation of the device for dividing by the example of the implementation shown in Fig.2.

A four-bit divider C co, ciC2C3C4 is fed to the input 5 of the divider, to the input 6 of the dividend - an eight-bit divisible A

530.3132333435363738, and the input 7 of the logical zero of the device is zero. It is assumed that the dividend and the divisor are positive normalized fractions (i.e.

co 0; ai ci 1). Since i A 1, j, the quotient Q qiq2qsq4qs is positive

a number lying in the range - Q 2, i.e.

qi is a whole part of this number.

The division is performed according to the algorithm without restoring the remainder, and each bit of QJ is a control signal for the next row of the matrix, i.e. determines which operation — addition or subtraction — must be performed on this line. In the device, the divider subtraction is carried out by adding the additional code of the number (-c) (the additional code is obtained by inverting all digits of the divider bits Cj with the elements EXCLUSIVE OR 24 and then adding the unit to the lower bit of the node 1 |). The first computation node 11 is controlled by the level of the logical unit coming from the input 11 of the device. At the input 12 of the correction device receives the level of logical zero, or (with repeated use of the device) the value from the output 13 correction device.

The remainder of Bi in each row of the matrix is calculated as two numbers: the number S and the number E, composed of bitwise Sn and bitwise n, respectively, formed at the outputs of the sums and transfers of single-bit binary adders 25 and 37 (the sum of these two numbers is equal to Bi).

The next bit of the private QI is determined by the value of the transfer from the higher bit of node 1i, taking into account that in the current remainder BM transmitted to the next row of the matrix in the two-row code in the form of bitwise 5m and bitwise bit transfers Ea , transfer to the highest bit of node 1m can be saved. which is signaled by the signal Km at the output of the body of the body Zm. Thus, the next bit qi at the output 8i of the node A is determined by the formula

qi Ki-rloi + (Km + loO-lTGi Go + TO-ITGI, where is the inverse transfer value to the highest bit of the calculator 1m generated at the output of the node Zm (output 72 cells 23);

Id is the transfer value from the high bit of the node 1 | generated at the output 44 of the transfer cell 22 of the high bit;

ITGI is the transfer value from the most significant bit of the computational node 1j, formed from the value of all bits of the two-row code of the remainder В |.

At outputs 9 and 10 of the quotient, a two-row code of the remainder is formed, which, if necessary, can be reduced to one-way with the help of a two-input

adder (this adder may be a system-wide tool).

If it is impossible to obtain all the private bits in one clock cycle, the device can also be used in multi-cycle mode, while the information from outputs 9 and 10 of the remainder, the correction signal from the output 13 of the device correction and the lower bit of the private output from the output 8t go to inputs 6 and 7 the dividend, the correction input 12 and the input 11 of the level of the logical unit, respectively (through the corresponding intermediate registers) to obtain the next group of quotient bits.

Claims (1)

The invention includes a dividing device containing m computing nodes, where m is the number of quantified private bits, m nodes forming the transfer generation and transit functions, m knots forming the high bit and m nodes forming the quotient, and the divider input of the device is connected to the inputs of the first group i-ro of the computational node (where i 1,2, ... m), the sum and transfer outputs of which are connected to the inputs of the first and second groups, respectively, of the 1st node of generation of transfer generation and transfer functions, low-order outputs the first and second groups of which are connected to the inputs of the first and second groups, respectively, of the 1st node of the transfer to the higher bit, the inputs of the higher bits of the dividend, and the device zero are connected to the inputs of the second and third groups, respectively, of the first computing node, whose setup input is connected to the input logical unit of the device, the input settings Q + 1) -ro computing node, where 0 1.2t-1). connected with the output of the j-ro node forming the quotients of the private, the inputs of the lower bits of the second and third groups (j + 1) of the computational node are connected to the inputs of the corresponding bits of the dividend and the device zero, respectively, the outputs of the nodes forming the quotient of the private device , characterized by the fact that, in order to improve the speed of the device, the inputs of the first and second groups of j-ro node forming the generation and transfer transfer function are connected to the inputs of the higher bits of the second and third groups (j + 1) -ro computational la, respectively, the first and second outputs residue devices are connected to the inputs of the first and second groups of m-ro assembly forming generation and transfer transit functions, devices correction output connected to the output of the mth transfer forming node significant bit, the output j-ro assembly forming transfer to the higher bit is connected to the correction input of the transfer function generation and transfer transit node, the correction input of the first transfer function generation and transfer transfer node is connected to the device correction input, the inputs of the first and second groups of the 1st private digit generation node are connected to the outputs of the first and the second groups of the 1st node of formation of the functions of generation and transit of transfer, respectively.  35 + J6 JJ FIG. 3 SPb 5