SU1300546A1 - Displaying device - Google Patents

Abstract

The invention relates to automation and computing and can be used in devices for the visual presentation of information. The purpose of the invention is to simplify the device. The goal is achieved by the fact that the device for indicating, containing the pulse generator 1, the primary binary counter 2, the binary-decimal counter 3, the register 4, the decoder 5, the indicators 6, the pulse distributor 7, the second binary counter 8 is entered, the switch 9, the driver pulses 10, the delay element 11 and the I K-trigger (L

Description

12. The operation of the device is based on dividing the binary number by 10 with fixing the remainder after each division in the binary-decimal counter AND indication of the remainder. The code of a binary number is entered into the first binary counter from the device input and the clock frequency from the pulse generator begins to flow to its counter input. The second binary counter works during this period on addition and calculates the pulses from the output transfer-. In the second binary counter, an integral part of the division of the initial number by 10 is recorded, and in the binary-decimal counter, the remainder of the division. The signal from the pulse driver triggers its state, the switch switches and the count direction of the first and second binary counters changes. Source conversion cycle

one

The invention relates to automation and computing and can be used in devices for visual representation in the decimal code of information prefused with a binary code at the input of the device.

The purpose of the invention is to simplify the device.

FIG. 1 shows a block diagram of a display device; in fig. 2 - timing charts of the device.

The device contains a pulse generator 1, the first binary counter 2, the binary-decimal counter 3, the outputs of which are connected to the information inputs of the register A, the outputs of the register 4, are connected to the inputs of the decoder 5, the outputs of which are connected to the information inputs of the indicators 6, controlling the inputs of which are connected to the outputs of the pulse distributor 7, the second binary counter 8, the switch 9, the pulse shaper 10, the delay element 11 and the IK-trigger 12, the information inputs of the device 13.

the binary number and its indication in decimal code ends at the time of the zeroing of both binary counters. The signal from the high-order output of the pulse distributor is inputted to n, the enable input of the first binary counter, the code of the initial binary number being entered into the first binary counter and the cycle is repeated. Introduction of a second binary counter, switch, pulse generator, delay element and trigger with their new connections to the device has reduced hardware costs by eliminating comparison circuits, AND group, OR element, and group of decimal meters. The cost of these nodes increases in proportion to the number of displayed bits of the number. The device provides an indication in the decimal number system of information represented by a binary code. 2 Il.

The operation of the device is based on the repeated division of the initial binary number by 10 with fixing the remainder after each division in the binary-decimal counter 3 and indication of the remainder. The entire part of the result after each division is stored in one of the binary counters 2.8.

Consider the operation of the device on the example of output to the indicators 6 of the information presented at the input of the device of the bit binary combination.

Let the input device post

number

25

N (111 001001) 2 (457),

At time t, at the input of the resolution of the installation of the first binary 20 counter 2, there is a logic level 1 coming from the pulse distributor 7 (Fig. 2a). Counter 2 records the code of the input binary number. 1K-trigger 12 is set to one (Fig. 2e), thereby counter 2 is prepared for subtraction, the second binary counter 8 is added, and the counting inputs of these counters are connected by switch 9 to generator 1 and transfer binary - a virtual counter 3, At the outputs of the transfer of binary counters 2, 8 - the level of logical O (Fig. 2e, g). The generator 1 is blocked by a signal from the second output of the form-jQ inputs of the indicators 6, to excite the pulse generator 10 (Fig. 2c, d).

at that, there will be one of them, to the control input of which, at a given time, the signal from the distributor of impulses 7 is received. Register 4 J5 enables display of the output information of Binary Counter 3 when counting pulses.

At time t, a short pulse appears at the first output of the driver 10 (FIG. 26), which rewrites the contents of the binary-decimal counter 3 to the register 4 and, through delay element 11, zeroes the counter 3 and converts the pulse distributor to the original (zero ) state. The 1K flip-flop 12 does not change its state, since at its IK inputs at this moment the combination 00.

After that, the shaper 10 removes the inhibit signal from the generator 1 (Fig. 2c; t), the input frequency of which begins to flow to the digital input of the binary-decimal counter 3 and through the switch 9 to the counting input of the counter 2 working on subtraction (Fig. 2d ; and ".

35

).thirty

The counter 8, operating in the considered time interval for addition, calculates the number of transfer pulses of the binary-decimal counter 3.

At time t, the 457th counting pulse arrives from generator 1, counter 2 is zeroed, at its transfer output a level of logical 1 appears. (Fig. 2e), the front edge of which starts the driver 10, the blocking generator 1 (Fig. 2c, d). At the same time, the number (7) u (the remainder of the first division) is fixed in the binary-decimal counter, 5 is the number (45), and g (the whole part). At 1K inputs of trigger 12, code 01 is set.

At time t, the number (4), on the first is 20, and in the binary-decimal counter 3, the number (5). which at time t is written to register 4 and fed to indicators 6. At time t, counters 2, 8 are reset, and binary-decimal counter 3 contains the number (4), which is then displayed on indicators 6 (FIG. 2, tg). This completes a one-time conversion of the initial binary number N (111001001) 2 for its visual representation in decimal code. However, if the device is intended to convert and display a higher-resolution number, the operation cycle continues. FIG. Figure 2 shows the case where the display device allows displaying a 5-digit decimal number.

With the arrival of the next short pulse from the first output of the imaging unit 10 (Fig. 2b; tg), the transfer output of the counter B immediately appears at the level of logical I, the leading edge of which is again started by the imaging unit 10, similarly at time t. Thus, after both counters 2, 8 on the generator 10 appears coiled, the generator remains blocked with a good pulse (FIG. 26), the register 4 of the binary-decimal counter 3 rewrites the number (7) ,, after this counter 3 is zeroed out, and the dispenser 7 goes to the next state. The trigger 12 is set to the zero state (d. 2d), thereby counter 2 is prepared for operation on addition, counter 8 is on

nb: m to the end of the cycle of operation of the device (Fig. 2d; Q). When the pulse distributor 7 of logical 1 appears in the higher-order pulse (Fig. 2a; ta), the binary number code N is output from output bus 13 to 13, the transfer output of counter 2 is set to zero (Fig. 2e; tj) . This ends

subtraction, and their counting inputs are connected by the switch 9, respectively, to the transfer output of the binary-decimal counter 3 and the output of the generator 1.

The information from register 4 is converted into a seven-segment code of the indicator by the decoder 5, is matched in level and fed to information

the inputs of the indicators 6, excited

at that, there will be one of them, to the control input of which, at a given moment in time, a signal arrives from the pulse distributor 7. Register 4 excludes the display of the output of Binary Counter 3 when counting pulses.

At time tj. (Fig. 2) counter 8 is zeroed, in counter 2 fic

The number (4) ,, is written, and in the binary-decimal counter 3, the number (5). which at time t is written to register 4 and fed to indicators 6. At time t, counters 2, 8 are reset, and binary-decimal counter 3 contains the number (4), which is then displayed on indicators 6 (FIG. 2, tg). This completes a one-time conversion of the initial binary number N (111001001) 2 for its visual representation in decimal code. However, if the device is intended to convert and display a higher-resolution number, the operation cycle continues. FIG. Figure 2 shows the case where the display device allows displaying a 5-digit decimal number.

With the arrival of the next short pulse from the first output of the imaging unit 10 (Fig. 2b; tg), the transfer output of the counter B immediately appears at the level of logical I, the leading edge of which is again started by the imaging unit 10, similarly at time t. Thus, after both counters 2, 8 are idle: m until the end of the cycle of operation of the device (Fig. 2d; Q). When the pulse distributor 7 of logical 1 appears in the higher-order pulse (Fig. 2a; ta), the binary number code N is output from output bus 13 to 13, the transfer output of counter 2 is set to zero (Fig. 2e; tj) . This ends

5 1300546

dyn cycle conversion and number indications. At time t, g, the distributor 7 enters the initial zero state. Shaper

re with go and co de yu scho ro de de ho ho 15 ry ne sc bi el co de ro co no no co

10, after time t, unlocks generator 1 and starts a new conversion and display cycle.

For stable operation of the device, the time delay (Fig. 26, c; t, -tj) of the end of the blocking pulse from the second output of the driver 10 relative to the pulse front at its first output must be longer than the switching time of trigger 12 and counters 2, 8.

To evenly illuminate the indicators 6, the duration of the blocking pulses of the generator 1 must be much longer than tj-t (Fig. 2),

The delay element 11 provides zeroing of the binary-decimal counter 3 after overwriting the information of register 4 and generating a short transfer pulse at time t (Fig. 2e), which is long enough to start the driver 10.

The positive effect of introducing a second binary counter, a switch, a pulse former, a delay element and a 1K flip-flop and new connections into a known device is to reduce the hardware cost for implementing the device for

display while maintaining a functional 35 is connected to the direction input

capabilities of the known device.

Claims (1)

Invention Formula A display device comprising a pulse generator, a first binary counter, a binary decimal counter whose bit outputs connected to the information inputs 45 inputs of the device. 0 the register, the outputs of which are connected to the inputs of the decoder, the outputs of which are connected to the information inputs of the indicators, the control inputs of which are connected to the outputs of the pulse distributor, characterized in that, in order to simplify the device, it contains a second binary counter, switch, pulse generator, delay element and 1K-trigger, IK-INPUTS of which are connected respectively with the transfer outputs of the second and first binary counters and with the first and second inputs of the pulse former, the first output of which is connected with a counting input of the 1K-flip-flop, with a register input and a delay element input, the output of which is connected to the reset input of a binary-decimal counter and the counting input of the pulse distributor, the second output of the pulse shaper is connected to the input of the pulse generator, the output of which is connected with the counting input of the binary-decimal counter and with the first control input of the switch, the second control input of which is connected to the transfer output of the binary-decimal counter, the third control input of the switch is connected with the counting input of the first binary counter and with the inverse output of the 1K flip-flop, the direct output of which is 0 five 0 accounts of the second binary counter, first and second outputs of the switch are connected respectively to the counting inputs of the first and second binary 40 counters, the output of the higher bit of the pulse distributor is connected to the enable input of the installation of the first binary counter, the installation inputs of which are information Editor H, Gorvat Compiled by A. Mescherkov Tehred A. KravchukKorrektor S, Cherni Order 1155/51 Circulation 434Subscription VNIIPI State Committee of the USSR for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, st. Project, 4