SU1290316A1 - Microprogram control device - Google Patents

Abstract

The invention relates to computing and can be used in microprocessor-based systems with firmware. The aim of the invention is to increase the speed of the device. The firmware control device contains two microinstructions memory blocks, a microinstructions register, a logic condition code register, a condition checking unit and a delay element. The purpose of the invention is achieved by combining the processing of logical conditions and the process of selecting the address of the next microcommand in the device. 1 hp f-ly, 4 ill. (L: about a

Description

The invention relates to computing and can be used in microprocessor-based systems with firmware.

The aim of the invention is to increase the speed of a twi device.

FIG. 1 shows a functional diagram of the device} in FIG. 2 - time diagram1 ") 1 device operation; Fig, 3 is a block diagram of the program; in fig. 4 - placement of microinstructions in memory blocks, corresponding to the algorithm.

The device contains the first 1 and second 2 blocks of memory of micro-instructions, the register of 3 micro-instructions, register 4 of the logic condition code, block 5 of condition check, delay element 6.

The condition verification unit 5 contains a decoder 7, a group of n elements AND 8, an element OR 9, an element NOT 10, the first 11 and the second 12 elements I.

In the initial state (Fig. 1 and 2) at the inputs of the Start, and Syncro, logical O. For the selection of the first microcommand

to the entrance impulse is given. ZO interfered with - LET: memory block 2. In Registers 3 and 4 are set to a signal NOT 10, i.e. Signal logic 1. The synchromesh of unit 5 is logic level O, therefore the outputs of elements 11 and 12 are also in the state of logic o. These levels keep the outputs of memory blocks 1 and 2 of microcommands off. Through the sampling time after the signal at the entrance You can apply a signal to the Syncro input to extract the first microcommand from the memory to the output bus. The first impulse from the Syncro input to the syncro input of block 5 passes through the element 12 and turns out to be on the permitting input B of the memory block 2. The outputs of this block turn on the working state and send the microcommand written to the zero address to the output buses. Thus, the first microprogram of the microprogram should be located at the zero address of the second memory block. The first operation cycle of the devices starts. The logic level 1 from input C hro, arriving at control input VK of register 3, turns off its outputs to the third state so that they do not

At the same time, the signal of logical 1 on the synchronous input C of register 3 takes place in this register of that information

evo state. The logical O signal at the input of the VC register 3, coming from the Syncro input, turns on the outputs of the register 3 to the operating state. Consequently, after setting the register 3 to zero, the zero code appears at address inputs A of memory blocks 1 and 2, in which the information is retrieved at this address. At the same time, the register 4 issues a zero code to the second group of information inputs of the condition checking unit 5. After this code is decrypted, decoder 7 appears at logical output 1 of decoder 7, at all other outputs — logical O. The zero output of decoder 7 is not used in block 5, therefore, logical O signals are set to logical O and the outputs of the group elements And 8-1, ..., 8-p. As a result, the output of the OR 9 element turned out to be a logical O signal. And 11 is closed to pass the signal from the synchronous input of block 5, and And 11 opens, since its first input is the inverted

interfered with - exit: memory block 2. In

element NOT 10 signal, i.e. logical signal 1. At the sync input of block 5 there is a logic level O, therefore the outputs of elements 11 and 12 are also in the state of logical O. These levels keep the outputs of memory blocks 1 and 2 of microcommands off. After a sampling time after the signal inlet Head. It is possible to send a signal to the Syncro input to extract the first microcommand from the memory to the output buses. The first impulse from the Syncro input to the syncro input of block 5 passes through the element 12 and appears at the enable input VC of the memory block 2. The outputs of this block turn on the working state and send the microcommand recorded at the zero address to the output buses. Thus, the first microprogram of the microprogram should be located at the zero address of the second memory block. The first cycle of the device operation begins. The logic level 1 from the Syncro input to the control input VC of the register 3 disables its outputs to the third state so that they do not

ZO interfered with - EXIT: memory block 2. In

At the same time, the signal logical 1 on the synchronous input C of register 3 records this information into the register

35 issues a memory block 2. State

register 4 is saved to not violate the enable signal of block 5 for memory block 2, after writing to register 3, you can

40 turn off the outputs of the memory block 2 and change the information in the register 4. For this, the signal at the Syncro input from the state d ogic 1 is set to the logical state O

45 As a result, the state of the logical O is set at the output of the element 12, which leads to the shutdown of the outputs of the memory block 2 to the third state, the code 4 is written to the register 4

50 transition control fields to the next microinstruction, the outputs of the register 3 are included in the operating state and give the same code to the input buses as the AND code just issued by the unit.

55 memories 2.

For example, let register 4 write the code n + 1 from the transition control field of the first micro-command.

312

This code from the outputs of register 4 is fed to the decoder 7. At the (n + 1) -th output of the decoder 7, a logical 1 signal appears. As a result, a logical 1 appears at the output of the OR element 9 and the element AND 12 turns out to be open. This means that in the next clock cycle after the arrival of the clock pulse, the enabling signal will be input to the VC input of the memory block 1, i.e. the second micro-command will be issued by this block from the cell whose address is specified in the first micro-command. At the moment of the reliable completion of the sampling of information in all the memory elements, a second impulse arrives at the sync syncro input - the second clock begins. Since in block 5 of the two output elements AND is open to this moment is element 11, the synchronous pulse passing through it is fed to the input B of the memory block 1. The outputs of memory 1 turn on in the working state and output the second microinstruction. At the same time, the outputs of register 3 are switched off to the third state and the recording of information in this register begins. The state of register A during the high level at the input of the Syncro does not change. With the start of the second clock cycle, the address inputs A of memory blocks 1 and 2 receive the address of the following microcommand — the selection of information at this address begins.

For example, let the transition from the second microcommand be conditional, i.e. to one of two possible microinstructions. The i-ro number of the feature by which the transition decision is made is encoded in the transition control field. Code i appears, like the second microcommand, at the beginning of the second bar. Writing code i to register 4 must be delayed until writing to register 3 is completed (as in the previous cycle). After the end of the recording in register 3 on the falling edge of the clock pulse, code i is entered in register 4 and from its outputs goes to the inputs of the decoder 7. After decryption, the i-th output of the decoder 7 enters the state 1, which goes to the second input (8-i ) -ro element I. (8-1) -th element I is open for passing a signal from its second input, which is connected to the i-th input Sign.

164

If the i-M input indicates a state of logical O, then the output of the element OR 9 will also have a state of logical O, which will lead to the opening of the element 12. If the i-M input. The sign will be a logical 1 state. Then element 11 will appear. In the first case, after the arrival of the sync pulse, the enabling signal will go to memory 2 (solid lines on the time diagrams in the third cycle - see Fig. 2), in the second - to the block memory 1 (dotted lines in the time diagrams in the third cycle - see Fig. 2), i.e. depending on the i-ro feature, a microcommand will be issued to the output buses either from the first or the second memory blocks (one at the output of the sign — from memory 1, zero-from memory 2). Reliable i- signal The ro sign must be formed by external devices (for example, an arithmetic logic unit) at the beginning of the third cycle and be maintained for a high level at the Synchron input.

If, for example, the i-th attribute is formed by an arithmetic logic unit based on the results of the second microcommand, then the time for this procedure is allotted to the maximum possible - the whole tact time. (Actually this time will be somewhat less by the amount of delay of the signal i-ro of the feature through the decoder 7 and the elements AND 8-i, OR 9, NOT 10, and 12). Thus, the address A of both microinstructions following the conditional branch is the same. Therefore, when placing a program in memory, it is necessary to first place pairs of microcommands following conditional transitions (in arbitrary order, with the exception of the zero addresses of both memory blocks and since the first microcommand of the program must be located in the zero cell of the first memory block). Then, also in an arbitrary order, it is possible to fill all the empty cells of both memory blocks with the remaining microcommands. The duration of the device cycle does not depend on the type of transition (conditional or unconditional), since it is determined only by the time of retrieving information from the memory.

at address A, and address A does not depend on the type of transition.

In the fourth cycle, a timing diagram is an example of a bar that was extended in duration. To do this, it is sufficient to delay the arrival of the next (in this case, the fifth) sync pulse. It is possible to stretch the clock both at the state of logical O at the input of the Syncro (as in Fig. 2), and at: the rest of the logical one. This circumstance removes the hard time synchronization restrictions.

Claims (2)

1. A firmware control device containing the first and second microinstructions memory blocks, the condition verification unit and the microinstructions register, the inputs of the logical conditions of the device connected to the first group of information inputs of the condition checking unit, characterized in that, in order to increase the speed of the device, the logical condition code and the delay element are entered, the outputs of the address code of the first and second microcommand memory blocks, the output of the address code of the first register are connected to the address inputs of the first o and the second microinstructions memory blocks and the first information input of the microinstruction register, the microoperations code of the first and second microinstructions memory, and the output of the microoperations code of the microcommand register are connected to the second (Informational microscopic register input and the output of the device microoperations code, the conditions of the first and second memory blocks mic The rocomand is connected to the information input of the logical condition code register, the outputs of the condition code of which are connected to the second group of informational}: inputs of the condition checker, the first and second outputs of which connected to the state control inputs of the first and second microinstructor memory blocks, the initial setup input of the device is connected to the reset inputs of the microcommand register of the logical condition code register, the device’s microinput is connected to the condition checker’s synchronous input, and the input of the logical condition code register the delay element, the output of which is connected to the control input of the record and the control input of the state of the outputs of the register of micro-instructions. 2. The device according to claim 1, characterized in that the condition checker comprises a decoder, a group of elements AND, the first and second elements AND, an OR element and an element NOT, the first group of information t inputs of the block connected to the first inputs of the AND elements the outputs of which, as well as the first output of the decoder, are connected to the inputs of the OR element, which is connected to the input of the element NOT and the first input of the first element AND whose output is the first output of the block, the first input of the second element AND connected to the code of the element NOT, the output of the second terminal; m This is the second output of the block, the second group of information inputs of the block is connected to the inputs of the decoder, from the 2nd to the (n + + 1) -th outputs of the decoder are connected to the second inputs of the AND elements of the group (where n is the number of logical - these conditions), the synchronous input unit is connected with the second input of the first element And and the second input of the second element I. Sign 1-1 l6jo9 1t9kt losslessness HcaoStnui Weasel Beadsaob transition transition transition nepexeS Fi & 2 .f. , N p vut. (Signs (Nachaao (Stop) MtfteimuKu Palais PolePol kova in us naMeffiai avreso Huxpoiintfauuu / lateiecnex ycjaauS dflOK memory I Micromaniao Mres cells, Field Field Code / South field / iOKu Pamvti avresa nirooperaiiy vecKia ycjietuii Z memory block X-npouiSoanHoe made Fiel Editor M. Bandura Compiled by V. Krivoruchko Tehred A. Kravchuk Proofreader E. Sirohman Order 7903/47 Circulation 673 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, st. Project, 4 Fig.Z Nikrdkonanva