SU1226454A1 - Dynamic microprogram device for controlling and checking - Google Patents

Abstract

The invention relates to automation and digital computing. The purpose of the invention is to expand the field of application of the device and reduce the amount of RAM equipment. The device consists of a random access memory of micro-commands, micro-command address registers, an address counter, triggers, a pulse generator, a switch, a delay element and a multiplexer. The aim of the invention is to reduce the amount of RAM by organizing the recording of two parts of alternative firmware in one storage unit, recording the first parts of the first firmware at forward addresses, and the second firmware at inverse, locking the recording of the corresponding program depending on the result of the branching supervisor algorithm. The invention can be used as local devices for control and management of parallel processes as microprogrammed control subsystems in multilevel data acquisition and processing systems, 3 sludge. g (L to HS about 4 cl.

Description

The invention relates to the field of automation, digital computing and can be used as local devices for monitoring and controlling parallel processes as microprogramming control subsystems in multilevel systems for collecting and processing information.

The aim of the invention is to expand the scope and reduce the amount of RAM equipment.

Figure 1 shows the functional diagram of the device; Fig. 2 is a timing diagram of operation of the device J in Fig. 3; an operation algorithm of the proposed device.

Dynamic microprogram unit for monitoring and control (Fig. 1) contains operative-storage device (RAM) 1 micro-commands, first micro-command address register (PAMC) 2, second micro-command address 3 register, micro-command register (RMK) 4 with fields: 4.1 addresses , 4.2 logic conditions, 4.3 micro-operations-, counter (MF) 5 addresses, trigger (Tr) 6 start, first - fourth (7-10) control triggers, 11 pulse generator, with the second 11.1 and first 11.2 outputs sync sequences t and 1, multiplexer 12, switch 13, elements AND 14-21, elements OR 22-24, Delay element 25, informational input 26 of the device, input 27 of the logic conditions of the device, output 28 of the device micro-operations, output 28.1 of the end of the RGMK operation, input 29 of the initial installation of the device, output 29.1 of the input entry 29, input 29.2 of the stop 29 of the input, input 30 of the device mode indication , input 30.1 of the write mode of input 30, input 30.2 of the read mode of input 30, input 31 of the write end mark of input 26, bus 32 inputs of control input 27, first to fourth inputs respectively 32.1 - 32.4 inputs 27 of the logical conditions of the device.

The proposed device operates R the following modes.

The first recording mode. In the Initial Position, all the memory elements are in the HVJioRoM state {s (chain cxfMi.r in the original with: t.tn gp {e

Ke P01, H-: 11M). G -Tbg TYA of the mouth G1ch1g TRYA NE264542

starts with the appearance of a single signal at the output 29.1 of the bus 29. With this start signal 6, it is brought to the single state. A single potential from its output enters the input of the generator I 1 and allows the formation of a grid of Jracto pulses. At the same time, a single signal is applied to the input 30, which, from output 30.1, sets trigger 9 to 1, which corresponds to the transition of the devices to the recording mode. ..The signal from the output of this trigger

ten

with a delay of G (element 25-delay), the synchronization pulses L from the output 11.2 of the generator 11 to the recording input of the operational storage device 1 are allowed to pass. On the first cp1-2 impulse 1-2, the microcommand is written into the operational storage device 1 at the zero address read from counter 5, through the open one through the single outputs of counter 5 switch 13. The switch 13 opens by the appearance of a single potential output element 25 delays. On the falling edge of the clock pulse L „from the output of the element And 19, the content of the counter 5 is increased by one. Further, as the microinstructions are written into the random access memory 1, the contents of the address counter 5 will increase: by one. At the end of the recording at input 31, according to Wits, a single signal of the end of recording mark. On the leading edge of the sync pulse 1, the last microinstruction of the microprogram will be recorded in the random access memory 1. On the trailing edge of the sync pulse (from the generator 11 output, the trigger 9 will go to zero state due to the presence of a single signal from input 31 on its R input.

-v

front of the next sync pulse. from output 11.2, the last address from counter 5 is written to register 3, due to the presence of a single pulse at the output of the element 14. Then the counter 5 is zeroed out after the expiration of c at the output of the delay element 25, the average potential disappears - the switch

13 closes. This ends the first recording mode. If necessary, the upper level control unit can issue a signal

15

20

25

Stop at the input 29, which from the input 29.2 through the element OR 22 will reset the trigger 6 start. As a result, generator 11 is turned off. In this case, the switch to reading is necessary to give a signal to Pusy to input 29. The second recording mode. In the initial state, all memory elements are reset. The device starts operation as in the first recording mode, Q recording. The difference is that the spray program is recorded in two stages. In the first stage, the first parts of the two firmware are recorded, and the first part of the firmware is recorded,

as in the first recording mode by addresses, chips are read from the single outputs of counter 5, and the first part of the second firmware is recorded at the addresses read from the inverse outputs of counter 5. The second stage consists in finishing the recording of the microprogram whose command to write is determined by the logic the condition of input 32.2 of bus 32. If the value of the logical condition is

input 32.2 is zero (one), the first (second) firmware is being written. The moment of the beginning of the recording of the first section of the second microprogram is the appearance at input 30 of a single recording signal, which from input 30.1 goes to the input of the trigger 9, sets its B to one state. In addition, the logic conditions at outputs 32.1 and 32.2 take a single

value. The signal at output 32.1 and the output of flip-flop 9 flip-flop 7 is transferred to one state through the open element AND 15. Through the OR element 23, at the falling edge of this signal, the unit from output 32.2 is recorded into flip-flop 8. Thus, single signals from the outputs flip-flops 7 and 8 open element AND 18. With a single potential from the output of this element, the inverse outputs of counter 5 of register 2 are connected to the switch. After the delay time has expired and element 25 through the open element I 19 on the leading edge of the sync pulse i- from output 11.2 s first microinstruction of the second firmware by ad- resu 55 read out from the inverse outputs of the counter 5, through the open switch 13. Further on clocks pro30

35

40

45

50

five

0

five

five

0

five

0

five

0

there is an increase in the contents of counter 5 and the recording of micro-commands of the first part of the second microprogram until the Stop signal at input 29 arrives. By this signal from output 29.2 through the OR 22 element, trigger 6 is reset. As a result, the generator 11 is turned off. This completes the first stage of the second recording mode. The second stage begins with the arrival of a single signal from the bus 32 of the control logic conditions at input 32.3, which, via AND 16, OR 23 elements, synchronizes trigger 8 to the falling edge. Logical information from this trigger receives the value of logical condition from input 32.2. As a result, if a unit is written to the trigger 8, the signal at the output of the element And 18 will be one, which corresponds to connecting to the switch 13 inverse outputs of counter 5 and register 2, if zero, then vice versa. Then the logical condition at input 32.4 of bus 32 takes a single value. The value of this logical condition determines the overwriting of the contents of register 3 into counter 5, which occurs if a single signal is generated at the output of the AND 20 element. After this, the Start signal is received at the input 29, which turns on the device synchronization. The sequential clock from output 11.2 through the element 19 and 19 records the next microcommand and increases the content of the counter 5 addresses by one. Recording is performed by direct or return addresses, which is determined by the logical condition at output 32.2 of bus 32. Thus, as a result of completing the second recording mode, one firmware remains in the random access memory, written at direct or inverse addresses. The end of the recording is similar to the first mode.

Microcommand reading mode. This mode starts either with a start signal on bus 29, the device has stopped recording, and without this signal, in the opposite case. Thereafter, bus 30 is supplied with a read signal, which, from output 30.2 of bus 30, sets trigger 10 to one state. Signal output

five

trigger 10 is enabled synchronization register register 4 sync pulses

1c of the output 11.2 of the generator 11 through the open element And 21. The same signal opens the switch 13 via the information outputs of register 2. If the recording occurred in the first mode or in the second mode the first microprogram was selected, the switch 13 opens to the direct outputs of the register 2, if the second firmware was selected in the second mode, the switch -13 is opened via the inverse outputs of register 2. The first micro-command is read at the zero (one) address written in register 2, - After the next sync pulse arrives ode 11.1 generator 11 into register

2 The address of the next microcommand is recorded. Address modification is made by multiplexer 12 and the element OR 24. Micro-operations are taken to the output 28 of the device. When a single signal appears at the output 28.1, the zeroing occurs, register 3 and triggers 6-10. This completes the read mode.

The application of the invention allows to reduce the amount of equipment and to expand the scope of application

reduce the amount of random access memory of a device by organizing the recording of two parts of alternative firmware in one storage unit

records of the first parts of the first firmware at forward addresses, and the second firmware at the inverse

blocking the entry of the corresponding program depending on the branching result of the supervisory algorithm.

Claims (1)

Invention Formula Dynamic microprogramming device for monitoring and control, containing a microinstructions random access memory, first address register, microinstruction register, address counter, start trigger, pulse generator, multiplexer, switch, first and second AND elements, first element OR, delay element, and input start-up of the initial set-up reset unit is connected to the S-input of the Trig 26454 6 a start trigger, the output of which is connected to the trigger input of the pulse generator, the first output of the pulse generator is connected to the first inputs 5 of the first and second elements I, the output of the first element I is connected to the recording input of the operative memory device of micro-commands, the group of inputs of the command code of the device connecting- 0 on with information inputs of the operative memory of micro-commands, the output group of which is connected to the group of information inputs of the register of micro-commands, 15 group of outputs of logical conditions, the output group The unmodified bits of the address output group, and the microoperations register group of microinstructions are connected, respectively, to the input group of the unmodifiable bits of the information input group of the first address register, the group of control inputs of the multiplexer and the device output group connected to the group of information inputs of the multiplexer, the output of which is connected to the first input of the first element OR, 30 output of a modified bit of the group of outputs of the address regis The microinstructions are connected to the second input of the first OR element, the output of which is connected to the input of a modified 5 bits group of information inputs of the first address register, a group of direct outputs of the first address register and an address counter connected to the first and second / SO groups of information inputs of the switch, whose output group is connected to the address input group of microinstructed random access memory, which is characterized by the fact that, in order to reduce the amount of RAM equipment and to expand the scope of application by providing parallel recording of alternative microprograms, iO it contains the second address register, the first - the fourth control triggers, the second and third OR elements, the third - the eighth AND elements, and the stop input of the group of inputs of the initial installation of the device is connected to the first input of the second OR element, the output of which is connected to the R input of the trigger start, the first output of the pulse generator is connected to the C input of the first control trigger and the first input of the third element And the output of the third element And connected to the first input of the fourth element And, the output of which is connected to the installation input the address counter, the group of inverse inputs of the address counter is connected to the third group of information inputs of the switch, the second output of the pulse generator is connected to the synchronization input of the first address register, the group of inverse outputs of the first address register is connected to the fourth group of information inputs of the switch, the group of outputs of the switch is connected to the information group the inputs of the second address register, the output group of the second address register is connected to the group of information inputs of the address counter, the first is four The third inputs of a group of inputs of the logic conditions of the device are connected respectively to the first input of the fifth element I, with the 3) input of the second control trigger, to the first input of the sixth element And and to the direct input of the seventh element And, the output of the seventh element And connected to the synchronization input of the counter address, the output of the fifth element K is connected to the S-input of the third control trigger, the output of which is connected to the first input of the eighth element And, the output of the eighth element And is connected to the inverse input of the seventh element And, and to the first control Odom switch, the third control output connected to a trigger the second input of the sixth element And, the output of the sixth element And is connected to the first input of the third element HJIli, the output of the third element OR is connected to the C input of the second control trigger, the output of which is connected to the second input of the eighth element And, the output of the fifth element And is connected to the second input of the third element OR, the input of the end of the group tag of the information inputs of the device is connected to the second input of the third element AND and the R input of the first control trigger, the record entry of the group The inputs of the device mode feature are connected to the S input of the first control trigger, the output of which is connected to the second input of the fifth And element, the inverse input of the third And element, and through the delay element to the second inputs of the first and fourth And elements and the second control input of the switch , the output of the third element. And is connected to the input. synchronization of the second address register, the input of the readings of the group of inputs of the device mode feature is connected to the 5th input of the fourth control flip-flop, the output of which is connected to the micro-register register sync input, the output of the end of the micro-register register operation is connected to the second-register address setup input, to the R-inputs of the second to fourth control flip-flops and to the second input of the second OR element, the output of the first AND element is connected to the counting input of the address counter, the fourth trigger output - the control is connected to the third control input of the switch, Janucti first part ftw-j pot f uKponfloioaMMtii ± fcmon cuf} poñuzai4uu I ± // ycx c4i4mbi8aHup J Implementing t unponpozpanA we -A- Editor T. Kugrsheva Compiled by V. Minakov Tehred V. Kadar Proofreader S. Shekmar Order 2134/48 Circulation 671 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, st. Project, 4 (HONSCH srig.Z