SU1290317A1 - Adaptive microprogram control device - Google Patents

Abstract

The invention relates to automation and computing and can be used as a control device for specialized digital computers used in automated control systems. The purpose of the invention is to increase the speed of the device. The device contains the address register 1, the first decoder 2, the first microcommand memory block 3, the logic conditions register 4, the first group of 5 AND elements, the buffer register 6, the second group of 7 AND elements, the fixing register 8 of autonomous firmware, the third a group of 9 AND elements, an OR 10 element, NOT a clock generator 11, a second delay element 12, a second counter 13 addresses, a second decoder 20, a second microcommand memory block 21, a comparison circuit 16, an adder 17, a fourth 24 group AND elements, first counter 19 addresses, third decryption Ator 14, the third block 13 of memory of microinstructions, the third element 22 NOT, the fifth element 23 And, the fifth group 18 elements And, the encoder 25, the counter 26 microinstruction, the third element 27 And, the first element 28 And, the first element 29 NOT, the fourth element 30, the second element 31 NOT, the first delay element 32, the second element 33 I. The goal is achieved by reducing the execution time of the microprograms on the linear sections. 1 il. L

Description

The invention relates to automation and computing and can be used as a control device for specialized computers used to control complex systems.

The purpose of the invention is to increase the speed of the device.

The drawing shows a functional diagram of the adaptive firmware control device.

The device contains the address register 1, the first decoder 2, the first microcommand memory block 3, the logic conditions register 4, the first group of AND elements, the buffer register 6, the second group of 7 AND elements, the fix execution register 8 of the microprogram, the third group of 9 AND elements, the element 10 OR NOT, clock generator 11, second delay element 12, second address counter 13, third decoder 14, third microcommand memory 15, comparison circuit 16, adder 17, fifth group 18 AND elements, first address counter 19 , second decoder 20, second block 21 yes mi microinstructions, the third element is 22 NOT, the fifth element is 23 AND, the fourth group is 24 AND elements, the encoder is 25, the counter is 26 microinstruction, the third element is 27 AND, the first element is 28 AND, the first element is 29 NOT, the fourth element is 30 AND, the second element 31 NOT, the first delay element 32, the second element 33 AND, the first input 34 of the device, the second input 35 of the device, the first 36, the second 37 and the third 38 outputs of the device.

The first input of register 1 of the address is to write to the address register of the first command from which the device starts working, the second input to set the address register in О, the third input to write to the register of the address of the second command from buffer register 6, the output to set addresses in block 3.

The first input of the first address counter 19 is for setting it to O, the second input for recording the address of the next microcommand from the combinational adder, the third input for recording the address of the first microcommand when the next command is executed by the device, the fourth input for incrementing the address by one with natural performing the next

five

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microinstructions The output provides the setting of the address of the next microinstruction in the second storage unit 21 and its supply to the input of the combinational adder 17.

The first input of the second counter 13 addresses is used to write the address of the first microcommand into it when executing the firmware of the program linear section, the second input is to increment its contents by one when the comparison circuit 16 is triggered, the third input is to set it to O. The output ensures that the next address is set microcommands stored in block 15.

The input of block 3 is designed to set the address of the next microcommand, the outputs - to set the indirect address of the next command in the buffer register 6, set the installation code in

Regarding the address register 1, setting the code of the checked logical conditions in register 4 of the logical conditions, setting the autonomy sign of the current microcommand, setting the number of the current firmware, setting the starting address in the third block 15.

The input of the second memory block 21 is designed to set the address of the next microcommand, to set the microoperations signals of the next microcommand, set the code controlling the subtraction of the unit from the contents of the microcommand counter 26 and add the unit to the first counter of the 19 addresses, output information in the execution register 8 of the autonomous firmware

The input of the third storage unit 15 is designed to set the address of the next mic | commands to set the offset with respect to the address of the 5th coded command read from

the second memorizing unit 21, setting the numbers of micro-commands relative to the beginning of the E1 of the complete microprogram, during which it is necessary to change the address of the next micro-command of the second block 21.

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five

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The input of the encoder 25 is designed to receive the current microprogram number, the first output to set the microcode code of the current firmware length code in the micro-counter, the second output to set the address of the first microcommand current microprogram.

The first input of the combinational adder 17 is for receiving the offset code from the third block 15, the second input is for receiving the address code of the next microcommand from the first counter 19 of the address, the output is for specifying the address of the sequential microcommand in the second storage unit 21 when the comparison circuit 16 is executed.

The third element 27 And is designed to issue a single control signal to the first element 28 And and the first element 29 NOT with the zero content of the microinstructor counter 26 The unit value of the control signal at the output of the third element 27 And may have in two cases (with the zero content of the counter 26 microinstructions): the direct inputs of the element 27 And are connected

with zero outputs of each of the resolution -20 firmware, and in the first counter

The DON counter of 26 micro-commands, the inverse inputs of the element 27 And is connected to the single outputs of each of the bits of the counter of 26 micro-commands.

The device works as follows.

In the initial state, all the triggers and registers except the memory blocks are in the zero state.

The operation of the device begins with the entry in register 1 of the address from the input 34 of the device to the address of the first command. The generator 11 clock pulses through the second element 12 of the delay and the fourth element 30 And when receiving the enable signal from the output of the third element 27 And corresponding to the zero content of the counter 26 micro-instructions, sets the first counter O of the 19 address, the second counter 13 addresses, register 4 logical conditions and buffer register 6, as well as the launch of the first decoder 2. The signal from the first decoder 2 from the first block 3 of the memory of micro-instructions reads the word corresponding to the first microprogram to be executed. omandy

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thirty

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19 addresses - the address from the first microcommand of the current firmware.

Simultaneously, from the fifth output of the first microcommand memory block 3, the first array address is stored in the second address counter 13, which stores information about changes in the microprograms included in the combined microprogram of the linear portion of the program.

After reading the information from the first block 3 of the micro-instructions memory, the pulse generator 11 through the delay elements 12 and 32, the first element 28 And opens the second group 7 And elements and allows the rewriting of information from the buffer register 6 to the address 1 regis.

After reading the information from the first block 3 of the microinstructions memory and writing into the counter 26 microinstructions the code of the length of the current firmware or the code of the length of the combined firmware, its readings are different from zero, therefore the signal at the output of the third element 27 And takes a zero value and through the first element 29 DOES NOT open the second element 33 and

or the first firmware to be executed - 50 through which the next clock name of the combined firmware of the program line section. By the signal from the first output of the first block 3 of these micro-instructions, the address register 1 is set to the zero state. The signal from the second output of block 3 of the microinstructions memory into the buffer register 6 records the indirect address of the next firmware number. WITH

The third output of the first block 3 of the microinstructions memory in the register 4 of the logical conditions is written down the code of the checked logical conditions.

At the same time, the signal corresponding to the current microprogram number or the first microprogram number of the combined microprogram when executing the linear section program from the fourth output of the first block 3 of the microcommand memory comes through the fourth group of 24 AND elements opened by a resolution signal from the output of 10 OR-NOT elements due to zero the state of all the outputs of the third group of 9 elements And, to the input of the encoder 25. From the outputs of the encoder 25, the counter of the 26 micro-instructions is recorded in the output of the encoder 25

19 addresses - the address from the first microcommand of the current firmware.

Simultaneously from the fifth output of the first block of 3 memory of microinstructions, the first address of the address counter 13 records the first address of the array that stores information about changes in the microprograms included in the combined microprogram of the linear portion of the program.

After reading the information from the first block 3 of the micro-instructions memory, the pulse generator 11 through the delay elements 12 and 32, the first element 28 And opens the second group 7 And elements and allows overwriting the information from the buffer register 6 to the address register 1.

After reading the information from the first block 3 of the microinstructions memory and writing into the counter 26 microinstructions the code of the length of the current firmware or the code of the length of the combined firmware, its readings are different from zero, therefore the signal at the output of the third element 27 And takes a zero value and through the first element 29 DOES NOT open the second element 33 And,

pulse generator 11 starts the second decoder 20 and the third decoder 14. Next, for each clock pulse of the generator 11, in accordance with the address recorded in the first counter 19 addresses from the second block 3 of the microcommand memory, the microcommands of the microprogram are read, and in accordance with with address

512

The words recorded in the second counter 13 addresses from the third block 15 of the microinstructions memory are read. Signals of micro-operations are read from output 37 of the second block of microcommand memory 21, the signal from the second output of the second microcommand memory block 21 opens element 23 and increases the content of the first address counter 19 by one, and also reduces the content of the microcommand counter 26 by one . The signals from the first output of the third block 15 of the memory of micro-instructions are received at the first inputs of the adder 17, the second inputs of which receive the address code from the first counter of the 19 addresses, as a result of summing these codes in the adder 17, the executive address of the next microcommand is formed. Signals from the second outputs the third block of memory of microinstructions 15 is fed to the first inputs of the comparison circuit 16, the second inputs of which receive a code from the output of the counter of 26 microinstructions. When these codes coincide, the output of the comparison circuit 16 is formed Igna the inputs of the fifth group 18 and the AND effective address microinstruction through fifth grup- ny AND gates 18 output from the adder 17 is recorded in the first counter 19 addresses. In addition, the control signal from the output of the comparison circuit 16 increases the content of the second counter 13 addresses by one and through the third element 22 does not prohibit the transfer of the unit from the second output of the second microcommand block 21 through the fifth element 23 to the input - New counter 19 addresses. With the arrival of the next clock pulse from the generator 11, the microcommand is read from the second microcommand memory block at the address rewritten into the first counter 19 addresses from the adder 17, and the control word and the cells with the number one greater than the previous one are read from the third microcommand memory block 15. . If the codes mismatched from the second output of the third block 15 of the microinstructions memory and the first counter of the 19 addresses are mismatched, elements 18 AND are closed, as a result of which the output address of the adder 17 into the first counter 19 of the addresses is not overwritten, the third element 22 DOES NOT open The second element 23 And and the control signal from the second output is second 7 6

The block of microcommand memory block 21 increases the content of the first counter of 19 addresses by one. When the counter of 26 micro-instructions is non-zero, the next clock pulse, as described above, reads the micro-instructions from the second micro-memory memory block 21.

During the operation of the adaptive control device, when a device receives the corresponding signal from the outputs of elements AND of the first group 5 at the second input 35 of the device, it is possible to change the readings of the buffer register 6,

After the completion of the execution of the next firmware, the reading of the microprogram counter 26 is zero. The pulse generator 11 through the elements 12 and 32 of the delay, the first element 28 And the second group of 7 elements And transmits the address of the following microcommand corresponding to the next microprogram or group of combined microprograms of the linear section of the program from the buffer register 6 to the address register 1.

The following pulse generator 11 through the second delay element 12 and the fourth element 30 and sets the first and second counters 19 and 13 of the addresses, respectively, the register 4 logical conditions and the buffer register 6. In addition, the start-decoder 2 is executed, read another word from the first storage unit 3 and the operation of the device is carried out similarly to that described.

In the case of reading from the first storage unit 3 words containing the autonomous firmware code or the combined autonomous microprogram code, the code corresponding to this microprogram arrives from the quad outputs of the first microcommand memory block to the inputs of elements 9 I. However, these elements are closed in -, that state, since the register 8 of the autonomous firmware execution commit is not recorded the code of this microprogram w. Therefore, the operation of the device continues as described. When issuing from the second block 21 of the memory of micro-commands, the code of the latest micro-command of the autonomous firmware on the third outputs of the second. a microinstructions memory block 21 a signal appears in the latch register 8

executing the autonomous firmware, the corresponding code is written.

If it is necessary to re-execute this firmware, the control signal from the output of register 8, latching autonomous firmware, and the signal from the fourth outputs of the first block of 3 microcommand memories will open the third group of 9 AND elements and output a signal to the third output of the device, which will read the result of the autonomous microprograms In addition, this signal through the first element 10 OR does NOT close the inputs of elements 24 AND the fourth group, prohibiting the recording of information in the encoder 25. Since the counter is 26 microc The command remains in the zero state, then the next clock pulse generator 11 through the elements 12 and 32 of the delay, the first element 28 And the second group 7 elements And transmits the indirect number of the next word of the first block 3 of the memory of micro instructions to the address register 1. Then the device works as described.

Claims (1)

Invention Formula Adaptive firmware control device containing the address register, the first decoder, the first microcommand memory block, the logic conditions register, the first AND group, the buffer register, the second AND group, the microprogram register, the third group of AND elements, the pulse generator , the first delay element, the first address counter, the second decoder, the second microinstructions memory block, the fourth group of And elements, the encoder, the microinstruction counter, from the first to the fourth And elements, the second element in the back The first and second elements are NOT, the command code and the start attribute of the device command are connected to the first group of information inputs of the address register and the installation input in the microprogram fix register, respectively, the output of the address register is connected to the information input of the first decoder, the output of which is connected with the address input of the first micro-memory block, the output of the reset indication is 0 five connected to the input of the O register of the register, the outputs of the indirect address field of the first microcommand memory block are connected to the first group of information inputs of the buffer register, the output of the logic conditions of the first microcommand memory block connected to the information input of the logical conditions register, whose outputs are bitwise connected to the first inputs of elements And the first group, py, the outputs of which are connected to the second group of information inputs of the buffer register, the second inputs of the elements And the first group are connected to By the conditions of the external conditions of the device, the outputs of the buffer register are bitwise connected to the first inputs of elements of the second group whose outputs are connected to the second group of information inputs of the address register, the outputs of the microprogram field of the first microcommand memory block are connected to the second inputs of elements of the third group, the outputs of the address field microprograms of the first memory block of microprograms are connected to the first inputs of the elements AND of the fourth group, the second inputs of which are connected to the output of the elements OR NOT, the outputs of the elements AND the fourth The second group is connected to the inputs of the encoder, the first output of which is connected to the first information input of the first address counter, the second 5 output of the encoder is connected to the information input of the micro-command counter, whose information outputs are connected to the inputs of the third And element, the output of which is connected to the first inputs of the first and the fourth elements And with the input of the first element is NOT, the output of the second delay element is connected to the second input of the first element And, the output of which is connected to the second inputs of elements AND of the second group, the second input of the fourth element I is connected to the output of the first and the input of the second delay elements, the output of the fourth element I is connected to the reset inputs of the first address counter, register of the logical conditions of the buffer register and the gate input of the first decoder, the output of the first element is NOT connected to the first 5 input of the second element AND , the second input of which is connected to the input of the first delay element and the output of the pulse generator, the output of the second element 0 0 0 And it is connected to the gate input of the second decoder, the information input of which is connected to the information output of the first address counter, the output of the second decoder is connected to the address input of the second microinstructions memory unit, the output of the microprogram memory register is connected to the information input of the microprogram register register, the outputs of which are output connected to the first inputs of elements AND of the third group, the outputs of which are connected to the inputs of the OR element and connected to the outputs of the indication of the firmware being executed by the device va, the output of the field of operations of the second microcommand memory block is the control output of the device, the output of the sign of the modification of the second microcommand memory block is connected to the input of the second element NOT, the output of which is connected to the counting input of the microinstruction counter, differing from in order to increase speed, it contains the second address counter, the third decoder, the third microcommand memory block, the comparison circuit, the adder, the fifth group of AND elements, the third element is NOT, the fifth AND element, and the output of the address field first block microinstructions connected to the information input of the second address counter, the reset input of which is connected to the output of the fourth Editor M. Bandura Compiled by A.Soshkin Tehred A. Kravchuk Proofreader T. Kolb Order 7903/47 Circulation 673.Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, Projecto st., 4 And, the information outputs of the second address counter are connected to the information input of the third decryptor, the gate input of which is connected to the output of the second element AND, the output of the third decoder to the address input of the third microcommand memory block, the output of the offset field is connected to the first input of the adder, the second input of which is connected to the information output of the first address counter, the output of the relative address field of the third microcommand memory block is connected to the first input of the comparison circuit, the second input of which oh is connected to the information output of the micro-command counter, the output of the comparison circuit is connected to the first 1 input of the second address counter, to the second inputs of the elements of the fifth group and the input of the third element of the HE, the output of the adder is connected bitwise to the first inputs of the elements of the fifth group whose outputs are connected with the second information inputs of the first address counter, the output of the third element is NOT connected to the first input of the fifth element I, the second input of which is connected to the output of the sign of the modification of the second microcommand memory block, output one of the item I is connected to the counting input of the first address counter.