SU1260965A1 - Device for registering sequence of execution of commands in programs - Google Patents

Abstract

The invention relates to computing, in particular, to devices for recording the results of program tests in digital data processing systems. The aim of the invention is to improve the speed of the device. The device contains a decoder of modes 1, four blocks 2, 3, 11, 12 And elements, two blocks 4, 13 of buffer memory, two blocks 5, 6 OR elements, six elements 7-10, 14, 15 And, trigger 16, two trigger 17, 18 with counting inputs, element 19 OR. 5 il. I (L N9 Od SO Od Slug 1 a

Description

The invention relates to computing, in particular, to devices for recording the results of program tests in digital data processing systems.

The purpose of the invention is to increase the speed of the device by enabling the tracing of large-volume programs, recording the sequence of command execution in programs.

FIG. 1 shows a block diagram of a device for registering a sequence of command execution in programs; FIG. 2 is a functional diagram of a mode decoder; in fig. 3 - functional diagram of the buffer memory unit; in fig. 4 - sequence of execution of commands of the analyzed programs; in fig. 5 - filling the buffer memory in various modes of the device.

A device for registering a sequence of execution of instructions in programs contains a decoder of 1 modes, the first 2, the second 3 blocks of the AND elements, the first block 4 of the buffer memory, the first 5 and the second 6 blocks of the OR elements, the first 7, the third 8, the second 9 and the fourth 10 elements And, the third 11 and fourth 12 blocks of elements And, the second block 13 of the buffer memory, the fifth 14 and sixth 15 elements And, the trigger 16, the first 17 and the second 18 triggers with counting inputs, the element OR 19, the group of inputs 25 of the transition address devices, inputs 21 of the mode code of the Device, group of inputs 22 addr The command of the device, the main 23 and an additional 24 inputs and the identification of the mode codes of the device, the input 25 read the device, the output 26 stop the device and the group of information outputs 27 of the device.

The decoder 1 mode has the first 34 clock input, a group of information inputs 35, the second 36 clock input, the second 37 and the first 38 outputs, the register of 39 modes, the decoder 40, the first 41 and the second 42 And elements, the first 43 and the second 44 OR elements, the delay element 45, the third element OR 46 and the third element AND 47,

The buffer memory block consists of a group of information inputs 28, a group of information outputs 29,

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read input 30, output 31 of the read information feature, the first 32 and second 33 write inputs, the OR 48 item, the delay element 49, the storage unit 50, the address counter 51, the number register 52 and the OR 53 block of elements.

The decoder 1 operates in three modes. The operating mode code enters a group of inputs 35 and is stored in mode register 39.

The code defining the first mode of operation comes from register 39 to the decoder 40, at the first output of which the resolving potential appears, and at the second and third outputs - inhibiting potentials. The permissive potential arrives at the first input of the first element AND 41. The incoming signal at input 34 in this case passes through the open first element AND 41, the first element OR 43 and the delay line 45 and enters the first output 38 of the mode decoder. When the decoder 1 is in operation in the second mode, a register is entered in the mode register 39 for a group of inputs 35, which generates the resolving potential at the second output of the decoder 40 and the inhibiting potentials at the first and third outputs of the decoder 40. In this case, the second element 42 opens. signal at input 34, it goes 5 Diet through the open second element AND 42 And goes to the first 43 and second 44 (elements OR. Pass the second element OR 44, the signal goes to output 37. After some time,

0 determined by the time of the delay element 45, a signal appears at the output 38 of the switch.

When the decoder 1 operates in the third mode, the mode register 39 in the group of inputs 35 receives a code that provides the generation of a resolution potential at the third output of the decoder 40 and the inhibitory potentials on the first and second outputs of the decoder 40, In this case, the resolution level goes to the third AND element 47, When a signal arrives at the TWZ or the first 34 input, it passes through the third element OR 46 and the third element AND 47 and enters the first 43 and second 44 elements of S1I. Further work of the decoder is similar to its work in the second mode.

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The buffer memory unit 4 operates as follows.

In the initial state, the address counter 51 and the number 52 register are reset to the zero state. Unit 4 is ready for operation.

Block 4 operates in two modes: write and read.

In the recording mode, the recording code enters the group of information inputs 28, passes through the block of elements OR 53 and is fixed in the register of the number 52. The signal arriving at the first 32 or the second 33 control input of block 4 passes the element OR 48 and enters At the input of block 50, this causes the code in register 52 of the number to be written to the zero cell of block 50. Then, after an interval of time determined by the delay element 49, the contents of the address counter 51 are enlarged, the address is ready for writing in the next code block 50. After the block 50 is filled, the address counter 51 overflows and the signal at the output 31 of the buffer memory 4 is exhausted.

In the read mode, signals for reading accumulated information are fed to input 30 of block 4. The first signal will go to the read input of block 50. At this moment, the contents of the address counter are zero. Consequently, the number register is 52; and, from block 50, a code stored at zero address is read out J5. Then, at intervals of time determined by the delay element 49, the contents of the address counter 51 are increased, the address is ready for reading from the next code block 50. After reading from the block 50 of the last number, the counter 51 of the address-overflows and a signal is generated at the output 31 of the block 4 of the buffer memory.

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In the initial state, the triggers 17 and 18 are reset. The trigger 16 is in a single state.,. At its direct output, there is a resolving potential, which opens the fourth block 12 of the elements I, the third 9, the fourth 10 and the fifth 14 elements of the first I. And the first 4 and second 13 blocks of the buffer are returned to the initial state. The second block 13 of the buffer memory is ready to receive the addresses of instructions of the program being analyzed.

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A device for registering a sequence of command execution in programs operates as follows. in a way.

When the device is operating in the first mode, the program being analyzed starts to be executed from the main program (SP) from the first address Ml, which is recorded in the zero cell of the second block 13 of the buffer memory. FIG. 4 each square means one address. The main program is executed without branching up to the instruction with the default M4, which is a conditional branch instruction. However, the transition condition was not fulfilled; therefore, control is transferred to address M5. Further, the main program is executed up to the instruction with the address M8, which is the next instruction for transferring the control, however its condition, as opposed to instruction M4, is fulfilled. The execution of the main program is temporarily stopped and control is transferred to the command A1 of the called program of the first level (EP). The transition address A1 is stored in the first cell of the second block 13 of the buffer memory. The record of the transition address is produced by the decoder 1 mode, which produces a signal at the output 38. This signal opens the first block 2 of the elements I. The code of the address of the transition from the operational register through the open fourth block 12 of the elements I enters the second block 13 of the buffer memory. The VP1 program is executed continuously until instruction A4, which is again a conditional branch instruction, in which the transition condition was fulfilled. As shown in FIG. 4, the VP1 program proceeds to the instruction with the address A7. This address is recorded in the second cell of the second block 13 of the buffer memory. Next, the VP1 program is executed to the end, and then control is transferred to the OP program at the place where the OP program was interrupted. Thus, the VP1 program transfers control to the main program cell at address M9. From this command, the continuous execution of the OP program continues until the end of instruction Ml 8. After the execution of instruction Ml 8, the program automatically switches to the program being called

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second level (tp2) address T1. After executing the instruction at address T1 of the VP2 program, it is sequentially executed to instruction T4, which is a conditional transfer control instruction, for which the condition is fulfilled and which transfers control to the first VP1 instruction program. The VP1 program is then executed linearly before the conditional transfer control instruction located at address A4. When the transition condition is met, control is transferred to the instruction at address A7. A further trajectory of the analyzed program can be traced in FIG. E. Thus, in the first mode of operation of the device, the addresses of instructions to which control is transferred are recorded in the buffer memory. The cells of the second block 13 of the buffer memory are successively filled with transition addresses in the order of execution of the analyzed program.

In the second mode of operation of the device, in block 13 of the buffer memory, not only the addresses of the transition are recorded, but also the addresses at which the instructions are located that transmitted the control (Fig. 5). Similarly to the first mode of operation of the device, the initial address Ml is initially stored in the zero cell block 13 buffer memory. Since the OT program is executed sequentially up to instruction M8 without transferring control, the command addresses change from Ml to M8 linearly with step 1, Instructions for address M8 is a control transfer instruction on condition that has already been executed. The address from which the control was transferred, and the address to which the control was transferred, are recorded in the adjacent cells of the buffer memory block 13. This happens as follows. Descrambler 1 mode with the arrival of the signal at the device input 34 first generates a signal at the second 37 output, which provides passage of the address from which control is transferred to the controlled memory register via the input command address group 22, the second block 6 of the OR elements and the fourth block 12 elements And in the second block 13 of the buffer memory. Then, the decoder 1 mode generates a signal at the first output 38, which provides the passage of the address to which the control is transferred from the operational register through the group 20 of the transition address, the second block 6 of the OR elements, and the fourth block of the 12 elements AND to the second block 13 buffer memory.

In the third mode of operation of the device 1v, the block 13 of the buffer memory records the addresses of all sequentially i instructions executed (Fig. 5). In this case, the decoder 1 mode generates signals at the outputs 37 and 38 when analyzing each instruction of the analyzed program.

Regardless of the mode of operation of the device, there comes a time when the second block 13 of the buffer memory is filled. In this case, the signal from the output 31 of the second block 13 of the buffer memory arrives at the counting input of the trigger 17 and sets it to one. B. As a result, the trigger 16 is set to the zero state. The second 9, fourth 10 and fifth 14 elements AND, as well as the fourth block 12 elements I. are closed. The first 7, third 8 and sixth 15 elements AND, and the third block 11 elements I. are opened. Potential from the output of the first trigger 17 It is passed through the element OR 19 and is fed to the output 26 of the interrupt device. Having processed the interrupt, the external device generates readout signals at the device input 25. These signals pass through the open sixth element 15 and enter the read input of the second block 13 of the buffer memory. As a result, codes appear on the group of information outputs of the buffer memory block, which pass through the first block 5 of the OR elements and enter the group of information outputs 27 of the device. The read signals at input 25 are generated until the interrupt signal is output at the device output 26. The signal on the device unit is canceled when the accumulations are overwritten in the buffer memory block 13 of the JS information on the output 31, a signal is produced that sets the trigger 17 to the zero state. At the same time, the addresses of the commans of the analyzed program lI begin to flow into the first block 4 of the buffer memory. The process of filling the first

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the buffer storage unit 4 is completely identical to the process of filling the second buffer storage unit 13.

Thus, the device simultaneously implements two parallel processes; the process of filling one buffer storage unit and the process of overwriting the contents of another buffer storage unit onto external media. After writing the last block of the buffer storage unit to the last cell, the address of the program being analyzed, it is switched to the rewriting mode of the accumulated information on external media. At the same time, another block of buffer memory, freed from information, is switched to the mode of receiving addresses of the analyzed program. When one block of buffer memory is filled during the program analysis, it is transferred to the mode of issuing information to external media, and another block of buffer memory is configured to receive information. Thus, the proposed device implements such an operation algorithm, which allows to obtain routes of the analyzed programs without losing information for a long interval of functioning of the computing system. This allows large programs to be laid out when using the device dp of recording the sequence of command execution in programs.

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Claims (1)

Invention Formula A device for registering a sequence of execution of commands in pro-40 grams containing the first block of OR elements, the first and second blocks of AND elements, the mode decoder and the first block of buffer memory, the group of inputs of the device transition address is connected to the first input of the first block of AND elements , the group of inputs of the device command address is connected to the first input of the second block of elements I, the inputs of the operation mode code of the device are connected to the information ones. the inputs of the mode decoder, the identification inputs of the device mode codes are connected respectively to the first and the second clock inputs of the decryphrato-55 with the second input of the first block of the mode element, the information output (the first block of the buffer memory is connected to the first input of the first block to s 0 five 0 five 0 5 0 OR elements, characterized in that, in order to improve speed, a second block of buffer memory, two triggers with counting inputs, a second block of OR elements, six AND elements, a third and fourth AND blocks, and an OR or trigger, with the first VYB mode decoder connected with the second input of the first block of elements And, the first inputs of the first and second elements And, the second output of the mode decoder is connected to the second inputs of the second block of elements And and the first inputs of the third and fourth elements And, the outputs of the first and second blocks of elements And are connected respectively to the first and second the inputs of the second block of elements of RSHI, the output of which is connected to the first inputs of the third and fourth blocks of elements And, the outputs of which are connected to the information inputs of the first and second blocks of the buffer, respectively am, the read input of the device is connected to the first inputs of the fifth and sixth elements, whose outputs are connected to the read inputs of the first and second blocks of the buffer memory, respectively; the outputs of the read information of the first and second buffer blocks of the memory are connected to the counting inputs of the first and second the flip-flops, the outputs of which are connected respectively to the single and zero inputs of the trigger and the inputs of the OR element, the output of which is the interrupt output of the device, the direct trigger output is connected to the second inputs By the third block of And elements, the first, third and sixth And elements, the inverse output of the trigger is connected to the second inputs of the fourth block of And elements, the second, fourth and fifth And elements, the outputs of the first and third And elements are connected respectively to the first and second recording inputs of the first the buffer memory block, the outputs of the second and fourth elements AND are connected respectively to the first AND recording inputs of the second buffer memory block, the information output of which is connected Commodity RSHI, the output of which is the information output of the device. J4 35 36 Phage 2 Jf l one 3f Jf JO 50 29 52 55 Fig.Z Havaffo, .L 1g. Editor L. Pchelinska Compiled by I. Sigalov Tehred L.Oleynik Proofreader E.Sirohman Order 5233/50 Circulation 671 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, Projecto st., 4 Mode 1 POKUMt femuM) til Ml MS Mi L1 H3 M H A7 Mf A8 MB Mff H7 M18 MB T1 A1 G4 A xr A3 "four Alt X7 AJ A9 M Tf H9 .five