SU1221652A1 - Instruction access device - Google Patents

Abstract

The invention relates to devices for prefetching computer commands to which high demands are placed on speed, hardware costs and power consumption. The purpose of the invention is to increase the speed of the device. For this purpose, the trigger 12 transition, encoders 14 and 15 of the ne25 X command are entered into the device. W gz O) iptjt.l

Description

transition and conditional transition, accumulating adder 5 and the third element I 8, the input and output of the encoder 14 are connected to the output of the command memory block 3 and the setup input of the trigger 12. The first and second reset inputs and the output of the trigger 12 are connected to the encoder's first output 15 and the reset input of the trigger 9 write and the installation input of the trigger 10 reading. The setup input, the sync input, the count input, the subtract input, the information input, the information output, and the transfer output of the adder 5 are connected to the first address input and synchronous input of the device, the output

one

The invention relates to digital computing and can be used in pre-sampling units, computer commands, which are subject to high demands for speed, hardware costs and power consumption.

The purpose of the invention is to increase the speed of the device.

FIG. 1 shows a block diagram of the device} in FIG. 2 shows an example of executing a transition instruction command; and in fig. 3 shows an example of the execution of the conditional jump instruction encoder.

The device contains (Fig. 1) counters 1 and 2 of the junior and senior addresses, blocks 3 and 4 of the memory of commands and the result, accumulating adder 5, elements AND 6-8, triggers 9-12 of writing, reading, indication of address and transition, circuit 13 comparisons, the coders 14 and 15 of the transition command and the conditional transition command, the first and second address inputs 16 and 17, the address sign output 18, the command output 19, the request input 20, the clock input 21, the synchronous input 22, the condition input 23, the information output 24, the first and second address outputs 25 and 26. The encoder 14 (FIG. 2) contains a decoder 27 and ale nt OR 28. The encoder 15 (Fig. 3) contains the decoder 29, the first element OR 30, group

the third element 8 and 8, the second outputs of the encoder 15, the output of the result memory block 4, the second input of the comparison circuit 13 and the second reset input of the address 11 trigger 11. The first and second inputs of the encoder 15 are connected to the output of block 4 and the input to the condition of the device. The first and second inputs and output of the And 8 element are connected respectively to the second output of the encoder 15, the output of the And 6 element and the output of the tracking device command. In addition, the device contains counters 1 and 2 junior and senior addresses and the second element And 7. 3 Il.

elements AND 31, the second element OR 32 and three elements AND 33-35.

Counters 1 and 2 are designed to count the lower and upper parts of the address of the next command selected from memory block 3 and form a single command counter. The memory unit 3 is for storing instructions. The memory block 4 is intended for intermediate storage of commands selected from block 3, and is a quick action memory block having separate write and read inputs. Accumulator-5 accumulator type 5 is designed to change the address of a command selected from block 4 when sequentially selecting commands, and calculating the initial cycle command when executing conditional jump instructions. It has an installation input, through which the initial recording of information is generated when a signal is sent to the synchronous input, a counting input (the low-order summation input), an information input that receives the code to be subtracted, a subtraction input, the signal from which the resolution to The implementation of this operation, the information output and the transfer output. Element 6 is designed to generate a command read signal when there is a request from input 20 and no trigger is denied from the output of trigger 10. The second element I 7 is intended to form recording signals in block 4 when there is a clock signal from input 21 and enable from the outputs of flip-flops

9 and 11. The third element And 8 is intended to prohibit the issuance of a signal accompanying the command to the output 19 when executing the conditional transition commands executed by the device itself for selecting the commands.

The trigger 9 is intended for the signal to prevent recording, if in block 4 there is no free space. Trigger

10 is designed to block the read inhibit signal if block 4 is empty. The trigger 11 is designed to issue a signal to the output 18 if the address of the entry in block 4 on the adder 5 turned out to be greater than the address on the counter 1. The trigger 12 is designed to transmit a signal if there is a transition command in block 4. Comparison circuit 13 is designed to achieve a signal when the codes at the outputs of counter 1 match.

and adder 5. The encoder 14 is designed to transmit a signal when writing to the block 4 transition commands. The encoder 15, when the conditional transition command appears at the output 24, produces a signal at the first output if the conditions from input 23 are fulfilled and the transition is necessary, and at the second output, reset to the initial state if the next command is executed. Single signals at the outputs of elements And 3 groups indicate that the conditions of this conditional transition command are fulfilled, i.e. transition is required. The signal at the output of element 34 is equal to 1, when A, 00-0, i.e. device in transition.

able to execute a command

Inputs 16 and 17 are used to record the command address in counters 1 and 2 and adder 5 at the start of the operation and during the execution of transition instructions. Addressing is accompanied by a clock signal from input 22, which reset triggers 9-11. The requests for the next command are received at the input 20, which stop after the signal from the output 19 is signaled that the command at the output 24 is ready. The input 21 receives a sequence of pulses from the generator, the period of which is equal to the access cycle to the memory. It is assumed that the signals at inputs 20 and

ten

20

25

221652

21 are shifted relative to each other. Outputs 25 and 26 receive the address of the command being executed. Moreover, if the output of signal 18 is 1, then the code 5 at output 25 must be reduced by 1 to obtain the actual value of the address. At the entrance 23 of the arithmetic unit receives signs, which may occur conditional transition.

The device works in the following way.

In block 3 of the memory there are commands to be executed. The device ...) 5 solves the initial state when applying the address of the initial command to inputs 16 and 17, followed by a clock signal from input 22. The higher bits of the address of the command are written to counter 2, and the low bits to counter 1 and adder 5. Except In addition, the signal from the output 22 sets the trigger 9 to state 1, and the triggers 10 and 11 to the state O. The signal from the output of the trigger 11 goes to output 18 and indicates that the code at the output of the adder 5 is not greater than the code at the output counter 1. The request signals from input 20 do not pass through AND 6 and do not satisfy It is, as unit 4 is empty. The signal from the input 21 (from the pulse generator), passed through the element And 7, enters the reading input and provides the reading of the command from block 3 to the address stored in the counters 1 and 2, and the falling front, having entered the recording input of block 4, writes this command to the address located in counter 1. In addition, the signal from the output of the AND 7 element increases the contents of counter 1 by 1, preparing the address of the next command, and also sets the trigger 10 to 1, allowing reading from block 4. If after the end of the next reading from block 3 it turns out that the code in the account Note that 1 coincides with the code in adder 5, block 4 is fully occupied. The trailing edge of the signal from the output of the And 7 element goes to the sync clock of the trigger 9, and since the output of the circuit 13 contains the signal 1, the trigger 9 will be set to the state O and close Element And 7. Filling

thirty

35

40

45

50

55

block 4 is terminated.

If block 4 is not empty, then the request for the command, passed through the element And 6,

enters the read input of block 4; as a result, the output 24 is considered to be the command stored at the address at the output of the adder 5, and the output 19 returns the output. The signal from the output of the And 6 element adds 1 to the contents of the adder 5, and by dropping the flip-flop 9, it allows the reading from block 3. If the reading on the block 4 results in a coincidence of the codes on the outputs of the counter 1 and the adder 5, then block 4 is completely selected. At the same time, on the falling edge of the signal from the output of the And 6 element, the trigger 10 is transferred to the state O, the And 6 element is closed, and the reading of commands is prohibited. As a result, trigger 9 is reset by the first read command from block 4, and trigger 10 by the first write command in block 4.

If block 4 is not empty, then the request for the command, passed through the element 6, enters the reading input of block 4, which ensures the reading of the command stored at the address at the output of the adder 5, at output 24 and arriving at the output of the 19th output. The signal from the output of the And 6 element adds 1 to the contents of the adder 5, and, resetting the trigger 9, permits reading from block 3. If the reading of block 4 results in coincidence of the codes on the outputs of counter 1 and adder 5, then block 4 is completely selected. At the same time, on the falling edge of the signal from the output of the element 6, the trigger 10 is transferred to the state O, and the element 6 is closed, i.e. reading commands is prohibited. As a result, the trigger 9 is reset by the first reading command from block 4, and the trigger 10 is reset by the first write command in block 4.

Consider the procedure for changing addresses in counters 1 and 2 and adder 5. In the initial state, the same code and adder 5 is entered into the counter 1 and adder 5 in the Accounts of the younger part of the address of the next command. Since reading from the cell of block 4 occurs only after writing information to it, the write address in counter 1 is greater than the read address in adder 5. In this case, the address of the next command to be executed is obtained at outputs 25 and 26, i.e. the higher address bits come from counter 2, and the lower 5

j O 5 0

from the adder 5. However, if the counter. 2 zeroed (00-0) and at some point there was an entry in block 4 at the last address 11-1 (the contents of counter 1), and the reading should come from the cell with the address 11-0, then the next pulse from the output of the And 7 element zeroes counter 1, the transfer signal of which adds 1 to the contents of counter 2 (0-01) and sets trigger one to 11. In this case, the code at the output of counter 1 is less than the code at the output of sum / mat 5 and to get a valid addresses of the next command 11-0, you must subtract 1 from the code in counter 2 (exit 25), as witnessed Signal 1 is output 18. Since the address of the next command is needed to execute a jump command relative to the current address of the command, the new address is generated in the arithmetic logic unit by summing the current address with the offset. Therefore, the subtraction of the indicated 1 does not cause difficulties. When in the above example the adder 5 overflows, the transfer signal resets the trigger 11, O turns out at output 19 and, therefore, the code at outputs 25 and 26 corresponds to the address of the next command.

Consider the operation of the device when executing a conditional jump command. Let the output of block 3 to the input of the encoder 14 receives the command conditional transition. The format of the command is shown in FIG. 2 and contains the operation code (CPC) and the offset relative to the current address D, and A. In the system of computer commands there can be several teams of conditional and unconditional jump (zero adder, overflow, etc.). If the decoder 27, having analyzed the operation code, reveals one of the transition commands, then the output of the OR element 28 appears 1. The signal from the output of the encoder 14 sets in one state the trigger 12, which puts the triggers 9 and 10 into the state corresponding to the complete filling of block 4 and keeps them in this state. As a result, writing to block 4 is prohibited (element 6 and closed), and reading time-: decided. After the next request for a command from input 20, output 24 of the transition command appears, which is fed to the input of the encoder 15 (Fig. 3) and the commands preceding the transition command are in block 4. To the second input of the encoder 15 from the input 23 of the device There are signs that can occur conditional transition. In this case, a signal 1 appears at the output of the decoder 29 if a transition command is received. If the corresponding condition is fulfilled (for example, O is contained in the arithmetic unit), then at the output of the corresponding element AND 31 of the group appears 1, which, having passed the OR element 32, enters the inputs of the elements 33 and 35.

The device can independently execute the conditional jump command if the transition occurs by no more than Aj 11-1 commands up the program, and the bit matches the digit of counter 1 and totalizer 5. In this case, all the commands preceding the conditional jump command, are in block 4. If A, 00-0, then at the output of element 34, a signal 1 appears, indicating the arrival of a conditional transition command, which the device itself can execute. If A, 00–0, then the signal from the output of the AND 34 element enters the input of the AND 33 element and at its output through W which 1 enters the input of the AND 8 element and closes it. As a result, this conditional branch command is not transmitted for execution. In addition, the same signal is fed to the input of the adder 5 and sets in it the subtraction mode. In this case, the offset code A received from the output 24 is subtracted from the contents of the adder 5. Thus, the adder 5 has the address of the initial cycle command written in block 4. The execution of the cycle is repeated. The repetition continues until a signal appears at the second output of the encoder 15, meaning that the вы sign indicating the conditional jump is absent and the command following the conditional jump command must be executed. In this case, the signal with. the output of the AND element 35 is reset trigger 12, and the trigger 10 is set to the state

corresponding to the empty block 4. Another way to exit this mode is to create a transition command, which the device does not execute by itself. Then the transition occurs in the usual way, i.e. carried out by recording the new content in the counters 1 and 2 and the adder 5 from the inputs 16 and 17, accompanied by the signal 22, which resets the trigger 12.

Claims (3)

1. A device for selecting commands containing a command memory, a result memory, a low address counter, a high address counter, a write trigger, a read trigger, an address sign trigger, two AND elements and a comparison circuit whose first input is connected to an information output the low address counter, and the output of the comparison circuit is connected to the information inputs of the write and read triggers, the information inputs of the low address counter and the high address counter are connected respectively to the first and second address inputs of the device, the sync inputs of the low and high address counters are connected to the device's synchronization, the information output of the low address counter is connected to the first address inputs of the command memory and the result memory, the information output of the high address counter is connected to the second address input of the command memory and the first address output device, output I the transfer of the low address counter is connected to the counting input of the high address counter and the installation input of the address attribute trigger, the output and the first reset input of which are connected respectively to the output address sign and device sync input, the first and second inputs of the first element And are connected respectively to the input for the device and the output the read trigger, and the output of the first element 1Y is connected to the synchronization input of the read trigger, the read input of the result memory, and the first setup input of the write trigger, the first and second the inputs of the second element I are connected respectively to the clock input of the device and the output of the recording trigger, and the output of the second element I is connected to the recording input of the result memory, the reading input of the instruction memory, the synchronization input of the recording trigger, the first reset input of the reading trigger and the count input of the junior the addresses, the second setup input of the write trigger and the second reset input of the read trigger are connected to the synchronous input of the device, and the information input and output of the result memory block are connected respectively to the output of the block memory of commands and information output of the device, which differs from the fact that, in order to improve speed, it contains a transition instruction encoder, a conditional transition instruction encoder, a transition trigger, the third element AND and accumulating adder, a setup input, a synchronous input counting input , the input of the subtraction, the information input, the information output and the transfer output of which are connected respectively to the first address input and the synchronous input of the device, the output of the first AND element, the first output of the encoder of the conditional branch instruction, output the house of the result memory unit, the second input of the comparison circuit and the second reset input of the address indication trigger; in addition, the information output of the accumulating adder is connected to the second address input .. of the result memory and the second address output of the device connected respectively to the output of the command memory and the installation input of the transition trigger, the first and second inputs of the Reset of which are connected respectively to the synchronous input of the device and the second output of the encoder of the conditional command th transition Ko tory connected to the third input of the read reset flip-flop, the flip-flop output junction is connected to the reset input. the write trigger and the setup input of the read trigger, the first and second inputs of the encoder of the conditional jump instruction are connected respectively to the output of the result memory and the input of the device condition, and the first and second inputs and output of the third And element are connected respectively to the first output of the jumper encoder, output the first element And the output of the accompanying device commands. 2. The device according to claim 1, characterized in that the transition instruction encoder comprises a decoder and an OR element whose input and output are connected respectively to the output of the decoder and the output of the encoder, and the input of the decoder is connected to the input of the encoder. 3. The device according to claim 1, characterized in that the conditional branch instruction encoder comprises a decoder, two OR elements, three AND elements and the AND element group, the first inputs of which are connected to the corresponding decoder outputs and the inputs of the first OR element, the decoder input is connected to the first to the input of the encoder, the second inputs and outputs of the elements AND groups are connected respectively to the second input of the encoder and the inputs of the second element OR, the output, the first and second inputs of the first element AND are connected respectively to the first output of the encoder, output Hilti second row element and the output of the second AND gate having inputs connected to the first input of the encoder, and the first and second input and an output of the third AND gate connected respectively to the outputs of first and second OR and the second output of the encoder. 23fig.Z Compiled by G.Vitaliyev Editor N. Volovik Tehred V. Kadar 1613/54 Circulation 671 Subscription VNIIPI USSR State Committee for inventions and discoveries t13035, Moscow, Zh-35, Raushsk nab., 4/5 Filial PPP Patent, g, Uzhgorod, st. Project, 4 Proofreader L. Patay