SU1367013A1 - Multiprogram control device - Google Patents

Description

with

9e

113

The invention relates to automation and computing technology and can be used in computing devices in the design of microprogramming devices with time-distributed functions, as well as in tools of the single-time service or in systems for calculating the service life of devices.

The aim of the invention is to extend the functionality by ensuring the issuance of control commands in various codes.

Fig. 1 shows the functional scheme of the device; FIG. 2 shows the format of the representation of the microprogram word; FIG. 3 is a timing diagram of a device control implementation.

The device contains a block J of operational memory, block 2 of permanent memory, trigger 3, multivibrator 4, registers 5 and 6, trigger 7, device start input 8, element OR 9, element 10, group 11, parameter code outputs , a group of 12 outputs of the parameter number, input 13 of the initial setup of the device, triggers 14, 15 and 16,

The operation of the device consists in the formation of time codes j reflecting the absolute time, expressed in terms of the frequency division factors of the master oscillator,

For example, the frequency of the master oscillator is 1.0 kHz, then the division factors for representing the absolute time can be accepted: 0, 1U, 10, 10, 6, 10, and t, e. At the same time, the first factor is hundreds of hertz, the second - tenths hertz, the third - units of hertz, the fourth - units of seconds, the fifth - tenths of seconds, the sixth g - units of minutes, and m, d,

The number of such coefficients realized by the device is determined by its resolution.

Each conversion coefficient determines the corresponding parameter, which. Displayed by the current parameter code value registered on trigger 7 and its (parameter) serial number registered on register 6,

In this case, for calculating the time resource, as well as for further description, it is advisable to take the parameter number for seconds 01e, for ten seconds - 02g, for minutes - 03g, for

32

ten minutes - 04 .., for hours - 05

oo

etc.

Thus, if the code 12.9 is fixed on groups 12 and 11 of the device outputs, then it should be considered that the resource counter at the moment of the microcommand Y indication displays for indication or another type of registration nine hours or 90 hours if codes 05, 9 and 06, Oh,

The device works as follows.

When the trigger signal arrives at the device input 8, the firmware (implemented in block 2) of the summation unit to the current value of the lower parameter is turned on.

After the end of the summation, control is transferred to the microprogram of analysis of the current value of the division coefficient of the transformation of the lower parameter by equality with the specified (assigned) division factor,

The functional purpose of the analysis firmware is to compare the current and specified division factors of the corresponding parameter, and, if they are equal, reset the current parameter and transfer control to the microprogram to add one to the current value of the higher parameter.

After the completion of the summation and analysis processes, control is transferred to the microprogram to output the value of the current account coefficients to the registration, after which the microprogram word is executed to reset the trigger 3,

When the next signal arrives at the device input 8, the operation is repeated in the specified order.

The current value of each parameter is represented by a sequential binary-decimal code fixed in memory block 1. In this case, the low-order bit (2 j of the lower parameter corresponds to bits with zero address; 2.2.2 bits correspond to RAM cells, respectively, with the first, second, third addresses. Four bits representing the value of the next parameter are located in RAM cells with addresses respectively 04, 05, 06, 07 and t, d,

The operation of the device is controlled using the firmware words recorded in block 2 of the permanent memory.

The structure of microprogram words is presented in Fig. 2, where A, is a group of bits serving

to encode the address of the next (relative to the executed) firmware word ;, Y-Y - control microcommands,

providing modes of operation of the corresponding functional elements; Y is a control microinstruction,

ensuring the operation mode of the unit; if Y U, information is being read from the cell of block I with the corresponding address, if y -l- write to the corresponding cell of block 1;

Yj - control microinstruction, providing reset of trigger 3 through the element OR 9; Y is a control microinstruction,

providing the unit during parameter processing (summation; to the information input of the RAM unit 1;

Y -Y - micro-command is the sync signal for recording information into the corresponding bits of the parameter register;

Y is a micro-command (sync signal) of writing the code of the parameter type into register 6; Yg - microcommand gating

element and 10; A. - group of ranks, employees

to encode the address of the cells of memory 1. The dynamics of the sampling of microinstructions, .т, е, the rate of speed) of the device operation, is provided by the multivibrator 4,

The period of operation of the multivibrator 4, determines the required duration of micro-commands,

The last edge of the time stamp from input 8, trigger 3 is set to one. High potential output from trigger 3 triggers multivibrator 4, which forms a series of clock pulses arriving. Hia entry control record buffer register 5,

0

g

,,

S

Q

-

0

five

0

On the leading edge of the clock pulse, microinstruction words from block 2 of memory are fixed on register 5. In each fixed microprogram elephant in the group of bits A, the address of the next microprogram word is specified (Fig 3, lines 5 and 4), i.e. transfer of control from one firmware word to another. The address of the next microprogram word may differ from the address executed per unit of the lower order, then the addressing of the selected words is done in the natural order. However, in the group of bits A, the address of any microprogram word can be programmed, in this case there is a galloping sample of microprogram words,

 Proceeding from the above, we consider the operation of the device when the subroutine is to sum up one to the current value of the parameter.

The summation procedure is performed at the firmware level. In this case, in order to simplify the device, there are no elements that perform the function of hardware summation; there is only one memory element of block 1, which stores intermediate values of all parameters.

When summing, the value of the least significant bit of the corresponding parameter is read from the corresponding block cell at the i-th step.

If the value of this bit is one, the block 2 address at the (.1 + 1} th step causes the corresponding mitcroprogram word to be read, which is used to write zero to the cell of block 1 with the same address, and control is transferred to the next microprogram word that reads from the next block address 1 of the next bit of the parameter being processed.

The next bit of this parameter is processed in the same way.

This sequence of actions is maintained until the current or next bit read from block 1 becomes zero,

If the value of the bit memory read from block J is zero, then using the corresponding executable firmware, the unit is written to the cell of memory 1 with the same address L, i.e. units instead of nui), and the control is transferred to the cell of the permanent memory unit 2, which determines the beginning of the analysis firmware according to the value of the younger parameter to the specified division factor.

For example, let the value of the minor

grams when analyzing the correspondence of the value of the lower parameter to the specified division factor. Let n 40 g (.table 2, steps 3 and 4).

The assigned I, the specified) division factor (conversion) of the corresponding parameter is set in an implicit way with the help of microinstructions.

parameter, fixed in block 1, Q conditional transition. In this case, the transition is equal to 9, and following it to the 01, to the microprogram word, then proceeding from a consistent evaluation of the equality or difference of the binary-decimal representation of the current and specified values of the corresponding information is distributed into the corresponding bit, Signals of block 1 are produced by the memory - g from the output of block 1, supplied to the table according to ti. 1, in which the pre-nth input of block 2 is through element. AND 10, the distribution of information is set in block 1 of the memory of the received parameter value.

those. The branching of the microprograms is performed by its own state of the corresponding information bit. 2 shows an example of the implementation of the second parameter parameter.

of the microprogram summation unit to the current value of the junior parameter.

In the first step of the zero cell

unit 1 of the memory, the zero value of k-25 is equal to ten, therefore, with

d, represented by a group of bits A 2; and also, with the help of a microgroup Yg 1, a gating element (AND III), one is read. Since the value of the next firmware word set by group of bits A is 02, the modified address of the next firmware word (2 is 102.

Firmware word at address 102 contains A 03g, A 00, Y 1, Y 5 O, therefore, in the second step zero is entered in the zero cell of block 1 (Table 1, line 1), and the control

transferred to the microprogram word of blocking the zero parameter, i.e. ka 2 with the address A 03 (Table 2, resetting the RAM cells with the addresses of 1 and 2). , branch O, 1, 2, 3.

When reading the firmware

the words at the third address of block 2 are the co-starting address of this microprogramme, which holds the address and control fields 45 A. 40g, then, when reading the mic recordable in register 5, it receives the rogrammed word from the ROM cell with

A value

with the same address we have: A, (;

Y 0. A 00; Y 0 ;. Yg 1. It means.

Thus, from the first cell, what is in the first step is reading the subunit 1 to the basic bit of block 2, according to gQ, the zero cell of the RAM, which

a zero signal is given, and control is transferred to the next firmware word with address 04 ' in which the address fields take the values A p; And Olg; Y 1; Y 1.

Those. the unit is written in the first cell of block 1, and the control is transferred to the nth address, where n is the value of the initial address of subproj.

in this case, it is equal to zero, it enters the input of the base address of the ROM, and then the value of the address of the next firmware word is U41d. Micro gg program word in the ROM cell with address 041 g contains (Table 3); BUT

 “-GJ A. Y, and; Yg 1, then in the second step of the firmware, i.e. from the RAM cell with address 01g.

conditional transition. In this case, the transition to the microprogram word, which estimates the equality or difference of the current and specified values of the corresponding bit, is produced by the signal from the output of block 1 supplied to the nth input of block 2 through the element .Al 10,

those. the branching of the firmware is performed by the own state of the corresponding information bit. In the basis of the given example, the established current value on the previous cycle is equal to ten, the specified cycle recalculation factor

0

five

comparing these values, the current value of the parameter should be reset to zero, and the transfer unit should be added to the higher bit.

Let us follow this with an example of the implementation of a specific firmware.

The analysis program consists of four steps. An example of the implementation of the firmware is given in table. 3

In cases not specified in the Comment section of the table, control is transferred to the information output routine with the starting address A .70 ,. where k is the start address of the subroutine

with the same address we have: A, (;

A 00; Y 0 ;. Yg 1. It means

in this case, it is equal to zero, it enters the input of the base address of the ROM, and then the value of the address of the next firmware word is U41d. Micro gg program word in the ROM cell with address 041 g contains (Table 3); BUT

 “-GJ A. Y, and; Yg 1, then in the second step of the firmware, i.e. from the RAM cell with address 01g.

a one is read (see Table 1; and the full address of the next MHKponporpaMNr of the word is A

142

i

Since the values of the first and second bits of the analyzed parameter correspond to the expected one, the control is transferred to the DDZ cell of the ROM for which the following field value is programmed in the cell with address 142 g: A 43g; A 2 02g;, Y 0; Yg 1, i.e. the value of the second RAM cell is read, and if this value corresponds to zero expected in this case), the control is transferred to the ROM cell with address 044 and from it to the cell with address K, where K is the starting address of the zeroing routine of the transformed conversion coefficient,

Otherwise, if the actual value of any bit was different from that presented, in Table. 1, instead of the named ones, the transfer control address would be formed respectively in 141, 42, 143 cells of block 2.88

The same content, equal to A 70, is programmed in these cells. All other microcommands, where A 70 is the initial address of the firmware for outputting information to the output of the device, are reset.

The program for resetting the corresponding parameter is presented in the table. 4 It has a starting address K (let’s accept K 60) and consists of four sequentially addressable microprogram words, in which respectively A, 61 "are fixed; BUT

AH

A, 63g and A 64

8 1 - 62 g; in the cell block

2, with address A 64, the group of bits A is assigned the value of m, where m is the starting address of the microprogram summation of the next, higher parameter,

In the remaining fields of all the firmware words of the zeroing firmware Y, and the block address; 1 - А 2, therefore, at each step takes the values: O, 1, 2, 3 - for the lowest parameter, or i, in general, (i + l), (i + 2) to (i + 3), where i is the address of the RAM cell, in which the lowest bit of the parameter being processed is stored.

Firmware output information on the output of the resource counter (Table 5)

r

 is carried out in 5 steps, where n is the number of processed parameters. In the first four steps, bits A of the buffer register indicate the address of the RAM cell containing the output information, with one of the micro YC, Y, or Y "taking the familiar Y, J. g,

Y or Y

i about 6 7

the unit, i.e. maintained with

10, the correspondence of the output information and the bit of the register of the parameter in which this information is recorded.

At the fifth step, the group of bits A. is used to program the number of the output parameter

15, which, by the microgroup Y 1, is fixed to register 6.

In this case, information on the register of the parameter number and on the register of the parameter is fed to the information inputs,

20 ee, the corresponding microcommands are supplied to the synchronous inputs.

For example, J 70d, then the subroutine of the output of the lower parameter, the value of which is fixed in

Table 25, 1, takes the form shown in Table. five,

Claims (1)

Invention Formula A firmware control device containing the first trigger, the AND element, the multivibrator, the OR element, the permanent memory block, two registers, and the trigger input of the device va is connected to a single trigger input, the output of which is connected to the input of a multivibrator, the output of which is connected to the write enable input of the first register; Formational inputs of which are connected to a group of outputs of the block constant n-. memory, the output of the first bit of the register, the gistr is connected to the first input of the AND element, different the fact that, in order to expand the functionality of the device by ensuring the issuance of control commands in various codes, a memory block is inserted into it, the third, fourth and fifth triggers, and the input of the initial installation of the device is connected to the first input of the SHS element, the output of which is connected to the zero input of the first trigger, the output of which is connected to the reset input in O of the first register, the first group of bit outputs of which is connected to the information group of the second register and the group of ad- the main inputs of the operational section, whose information input is connected to the second bit output of the first register, the third bit output of which is connected to the write enable input of the second register, the group of bit outputs of which is a group of device parameter number outputs, the second the group of the bit outputs of the first register is connected to the inputs from the first through p-3) -th group of address inputs of the permanent memory unit, the fourth bit output of the first register is connected to the second input of the OR element, the fifth bit output d of the first register is connected to 0001 (K) O and O OO 0102002 O O OO the input of the write resolution of the RAM, dough, seventh, eighth and. the ninth bit outputs of the first register are connected to the sync inputs of the second, third, fourth and fifth triggers, respectively, the information inputs of which are connected to the output of the RAM block and the second input of the I element whose output is connected to the nth input of the address group the inputs of the fixed memory block, the outputs of the second, third, fourth and fifth triggers are respectively the first, second, third and fourth outputs of the group of device parameter code outputs. a 1 table 2 Entry to the firmware summation Reading the contents of the zero cell RAM, Care at 102 address, if the contents of RAM is 1, or - at 02gadres, if the content of RAM is O 07.40 00 1010 and. about 10203001000 030401о о о о о 0440О 101оооо 10405011000оо 0506. OH00 00oooo 0640021010О00 10607021000 071003О О and О ten 4003 1010 BY I03100 Note In the event that the value is the eleventh address of the ROM, the browser. 14U0041О and О О 41 01 42.GOOD 2 4 00700000 142 00700000 14202430000 4303KO О О О О 14300700000 . about oo oo oo 00 OO 00 o - Write the unit to the zero cell of RAM and care to 40. address of the ROM. ABOUT 0Record zero in zero cell of RAM and care for 03d address of ROM at 1Reading the contents of the first RAM cell. Care at 104 address if A, yj 1, or PA 04 address ROM, if A 0 О Write the unit to the first cell of RAM and care to 40 address of the ROM 0. Write zero to RAM cell and care on 05, address ROM 1Reader the contents of the second cell of RAM, Care for the address of the ROM address, if Ld,; , or at 06 address ROM, if L.0 О Write the unit to the second cell of RAM and care for 40 address of the ROM 0Record zero in the second cell of RAM to care on 07 address of the ROM 1Reading the contents of the third RAM cell and care for the 110 address of the ROM, if A j03y-, or 10 for the address of the ROM, if, 0 О Write a unit in the third cell of RAM and care for 40 address of the ROM О Write zero in the third cell of RAM and care on the 11th address of the ROM of all bits of the parameter one, the control is transferred to which the sampling of the unit to the next parameter is started. Tavlntsa 3 . ABOUT ABOUT ABOUT about about 1 1 about about 1 one about Analyze content 2 bit lower parameter. If 2, then go to the 4. address of the ROM, so the junior bit assigned S-0 Analysis of content 2 bit. If 2 1, then go to the address of the ROM, as it follows) by weight of the discharge assigned to K. 1 Analysis of the contents of 2 p "erda" If 2 O, then the transition to the u3j address of the ROM, since cneAjTOHiwfl by weight of the bit of the mama K- ° C uo 00 T bl “pa k -Table 3 You “od 2 raerhda RAM Vshod 2 bits yes RAM Output 2 bits yes RAM Vyod 2 bits yes RAM Output type parameter Displays other parameters. It is produced similarly Inkhroiando word and trigger trigger 3 12 p p-1-2 6 I 13 Phie.1 eleven TO Fi8.2 Sh.ina 8 Devices (metna burden ). I tv.i. LmultiVi5rator 4 output ROM output 2 AO Output bu (regnoy register 5 Editor N.Ivydka Tehred A. Kravchuk Order 6840/48 Edition 704Subscription VNIIPI USSR State Committee for inventions and discoveries 133035, Moscow, Zh-35, Raushsk nab, 4/5 Fig.Z Proofreader O. Kravtsov