SU1288757A1 - Buffer storage - Google Patents

Abstract

The invention relates to computing and can be used in memory-storage devices of the system for entering information of multichannel measuring complexes. The purpose of the invention is to increase the reliability of the device. It contains the drive 1, multiplexer 2, selectors 3, elements AND 4, registers 5, elements AND 6, counters 7 words, element OR 8, triggers 9, elements AND 10, driver 11 pulses, block 12 priorities, element 13 delay, element OR 14, delay element 15, counter 16 write addresses, counter 17 read addresses, control inputs 18, 19 and 20. Write to 00 00 cd

Description

information words to the accumulator 1 at the addresses of the counter 16 are carried out after the analysis by the selectors 3 of the channel number contained in the word, and the blocks 12 of the signal. The content of the counter 16 is increased by one. Counters 7 count the number of words of each channel. Counters 16 store the address values for which the first word of the respective channels is stored. When reading on the clock pulse, the output of the counter 17, which belongs to the channel with the most

one

The invention relates to computing and can be used in the storage devices of data input systems of multichannel measuring systems.

The purpose of the invention is to increase the reliability of the device.

FIG. 1 shows a functional diagram of the buffer storage device; in fig. 2 is a word count diagram; in fig. 3 is a diagram of the record address counter; in fig. 4 is a schematic of a read address count.

Buffer memory device contains a drive 1, multiplexer 2, selectors 3, elements AND 4 groups, registers 5, elements AND 6 groups, counters 7 words, element SH1I 8, triggers 9, elements AND 10 groups, driver 11 pulses, block 12 priorities , delay element 13, OR element 14, delay element 15, write address counter 16, read address counter 17, control inputs 18, control inputs 19 and 20.

The number of selectors 3, elements And registers 5, elements And 6, counters 7 words, triggers 9, elements And 10, and counters 17 corresponds to the number of information receivers connected to the buffer storage device. The selector 3 can be filled into RAM or ROM. The address inputs of the RAM (ROM) are the inputs of the selector, and the information outputs are the outputs of the selector.

the highest priority is connected to the address inputs of accumulator 1. The read word is written to the corresponding register 5. At the same time, the contents of counters 7 and 17 are reduced by one. At the next clock pulses, words are read at the addresses determined by counter 17. Words are analyzed by selector 3 and, in the case of ownership, the channel is written into the corresponding register 5 and output to the output. 4 or about

five

five

.

0

Counter 7 words contains a counter. 21 and the element OR 22 (Fig. 2). The summing and subtracting inputs of the counter 7 are connected to the summing and subtractive inputs of the counter 21, the outputs of which are connected to the inputs of the element OR 22, OUTPUT - connected to the output of the counter 7 words.

The counter 16 of the address of the record contains the counter 23 and the elements AND-NOT 24 with open collector outputs (Fig. 3). The counting input of counter 23 is the counting input of counter 16, and the outputs are connected to the first inputs of the AND-24 elements and the second group of outputs of the counter 16. The second inputs of the AND-NOT elements 24 are connected to the control input of the counter 16, and the outputs are outputs the first group of counter 16.

The read address counter 17 contains a counter 25 and NAND elements 26 with open collector outlets (Fig. 4). The counting input, the information inputs and the write input of the counter 25 are respectively the counting input, the information inputs and the write input of the counter 17, The outputs of the counter 25 are connected to the first inputs of the AND-NOT elements 26, the second inputs of which are connected to the counter input of the counter- 25, and the outputs are the outputs of counter 17.

The device works as follows.

Before operation, the device is reset.

Triggers 9 are set to a single state, the word counters 7, the count .16 write addresses and the counters 17 of the cross-connect addresses are zeroed (the initial setting circuit is not shown in Fig. 1). Information words enter the input of the buffer mop-up device, the group of bits of which contains the address of the information channel to which these words belong. Processing units connected to the inputs of the buffer memory device receive information belonging to a specific set of channels. The proposed device is allocated to information processing units depending on its belonging to one or another channel using selectors 3. In memory cells of the selector 3, whose addresses coincide with the addresses of information channels assigned to the processing unit, logical 1 is recorded. In the rest of the memory cells, a logical O should be recorded. When implementing the selector 3 in the form of RAM, before starting work it is necessary to load into its memory a program for allocating information channels.

The information word is fed to the information inputs of the drive 1, accompanied by a signal at the input 20 of the device. At the same time, at the first output of the priority block 12, a logical 1 signal is formed, which connects the counter of 16 write addresses to the address inputs of accumulator 1, and the inputs of selectors 3 through multiplexer 2 to information inputs of accumulator 1. If the word of this information channel is to be replaced the processing unit, the signal of the logical 1 is set at the output of the corresponding selector 3 (the signal of the logical O is set at the outputs of the remaining selectors 3)

The signals from the selectors 3 are fed to one of the inputs of elements 6. The signal from the first output of the priority block 12 is delayed by the delay element 13 and fed to the input of the driver 11 pulses, which on the leading edge of the delayed signal forms a gating pulse to other inputs of elements AND 6. At the outputs of elements AND 6, on one inputs of which

the signal of logical 1 is present; pulses are formed, which increase along their falling edge of co. held by the corresponding counters 7 words and fed to the inputs of the element OR 8. The signal from the output of the element OR 8 writes the information word to the drive 1 and modifies the counter on the falling edge

16 addresses of record.

When the following information words arrive at the device input, the process is repeated. Thus, information is recorded in drive 1 at increasing addresses determined by the counter 16 of the write addresses, and the word counters 7 take on the values corresponding to the number of words accumulated for output at each output of the device. If the content of any counter 7 words is zero, i.e. In drive 1, there is no information to be stored on this output, the logical O signal from the output of such a counter closes the corresponding AND element 10 and allows overwriting the value of the 16 write address counter into the corresponding read address 17 counter. As soon as the value of the counter 7 words becomes non-zero, i.e. for this output, information appeared in accumulator 1, overwriting the value of counter 16 into the corresponding counter

17 is forbidden and its value corresponds to the address at which the first word to be output on this output is stored in drive 1.

From the outputs of the counters 7 words, the values of which are not equal to zero, the signals of logical 1 are fed to the inputs of the corresponding And 10 elements, which are opened by the signals of logical 1 from the outputs of flip-flops 9.

When a clock signal appears at the input 19 of the device, the signals from the outputs of the elements And 10 arrive at the inputs of the priority unit 12, which selects the priority one from all the signals of the logical 1 at its inputs and generates a signal corresponding to

output to him. In this case, the corresponding counter 17 is connected to the address inputs of accumulator 1, the information word is read out from accumulator 1. Multiplexer 2, when its control input does not have a logical 1 s signal, first output of priority unit 12, connects the accumulator 1 outputs to selector inputs 3.

If the information word on the output of accumulator 1 should be

to the output of the device, the corresponding selector 3 generates a logical signal. 1, the input to the input of the corresponding element is AND 4, the other inputs of which receive a logical 1 signal from the output of the priority unit 12 and the same signal delayed by the delay element 15. The signal from the output of the AND 4 element writes the word read from accumulator 1 into register 5, reduces the content of the corresponding counter 7 words per unit, resets the corresponding trigger 9 to the zero state and closes the corresponding element 10. And at the falling edge of the signal at the corresponding output of the block 12, the counter 17 is incremented by one, taking the value of the next address.

If the word read from accumulator 1 is not eligible, then a logical O signal is generated at the output of the corresponding selector 3, which closes the corresponding element 4, and the next signal at input 19 repeats the process until the word selected by the selector is read 3, or eoder-} the word corresponding to the counter of 7 words will not be equal to zero. The process is then repeated for the next priority input of block 12.

Requests to read the next informationdona words come asynchronously from the processing units to the inputs 18 of the device and set the corresponding triggers 9 to one state, opening the corresponding And 10 elements to them.

Claims (1)

Invention Formula A buffer memory containing a drive whose information input is the information input of the device, the output of the storage device is connected to the information inputs of the registers whose outputs are the outputs of the device controlling. the inputs of the registers are connected to the first inputs of the corresponding trigger and word counters, the outputs of which are connected to the first inputs of the corresponding readout address counters and elements AND of the first group, the second inputs of which are connected to the outputs of the corresponding triggers, the second inputs of which are the control inputs of the device group The third inputs of the And elements of the first group are the first control device input, element outputs And the first group is connected to the inputs of the priority block group, whose input is the second control input of the device, the outputs of the priority block group are connected to 1 second inputs of the corresponding read address counters, the third inputs of which are connected to the first output of the write address counter, the first input of which is connected to the output the block of prioritizers, inputs of the write address counter and read address counters are connected to the address inputs of the accumulator, the control input of which is connected to the second input of the address collector recording and to the output of the first OR gate, whose inputs are connected to second inputs of F words counters, selectors, on t l u Q that, in order to increase the reliability of the device, it contains a multiplexer, the second and third groups of AND elements, and the second delay elements, the second OR element and the pulse shaper, the input and output of which are connected respectively to the output of the first delay element and to the first inputs elements and the second group, the outputs of which are connected to the second inputs of the corresponding word counters, the first inputs of the elements AND of the third group are connected to the corresponding outputs of the group of the priority block and to the inputs g of the second element OR, the output of which is connected to the input of the second delay element, the output of which is connected to the second inputs of the elements AND the third, the group whose outputs are connected to „The inputs of the respective registers, the third inputs of the AND elements of the third group are connected to the second inputs. corresponding elements And the second group and the outputs of the corresponding selectors whose inputs are connected to the multiplexer output, the first and second inputs of which are connected respectively to the information input and output of the drive, the third input five 12887578 the multiplexer is connected to the output connected to the input of the first element of the priority block whose output is delayed. FIG. 2 (. Editor V. Petrash Compiled by S. Shustenko Tehred V. Kadar Proofreader A. Obruchar Order 7813/50 Circulation 611 Subscription VNII1Sh State Committee of the USSR for inventions and discoveries 113035, Moscow, LS-35, Raushsk nab., d, 4/5 Production and printing company, Uzhgorod, st. Project, 4    f Tszig.Z   " 26 Jj h v figl