SU1287135A1 - Generator of composite function - Google Patents

Abstract

The invention relates to digital computing and can be used in digital computing complexes, automation devices and computing. The aim of the invention is to extend the functionality of the imager by reconfiguring the channels for issuing a complex function. The shaper of a complex function contains a control block 1, a register 2 of information, a demultiplexer 3, a register of 4 addresses, a generator of 5 clocks, a counter 6, a group of N blocks 7.1 ... 7.N RAM, switch 8, N-1 adders 12.1 ... 12 (N-1), register 13 Settings. The generated function can be converted to analog form with the help of digital-analog converters 11.1 ... 11.N in each of the N channels. 2 Il. with

Description

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The invention relates to digital computing and can be used in digital computing complexes, automation devices and computing techniques.

The aim of the invention is to extend the functionality of the former by reconfiguring the channels of the complex function.

FIG. 1 is a functional diagram of a complex function shaper in FIG. 2 is a control block diagram.

The shaper of a complex function (Fig. 1) contains a control unit (CU) 1, an information register 2, a demultiplexer 3, an address register 4, a generator of 5 clocks, a counter 6, a group of N memory blocks 7.1 - 7.N, switch 8, containing N demultiplexers 9.1 - 9.N and N elements OR 10.1 - 10.N, N digital-analog converters 11.1 - 11.N, (N-1) adders 12.1 - 12 (N-1), register 13 settings, input tires 14.1 - 14 (N-1), control input 15, output tires 16.1 - 16.N shaper.

The demultiplexer 9.1 (, N) contains a decoder and a block of elements I. Depending on the tuning code that arrives at the control input of the demultiplexer, the information from the input is post. tupit on one of the N outputs of the demultiplexer.

The control unit 1 (Fig. 2) contains the control register 17, the mode (operation) trigger 18, the first 19 and the second 20 groups of elements I.,

Shaper complex function works as follows.

The device can operate in two modes: Preparation and Operation.

The Prepare mode is used to enter information corresponding to the reproducible functions into blocks of RAM 7.1 to 7.N and is set by a single signal at the first output of control unit 1.

The choice of the mode of operation of the former is determined by the arrival of the control signal on one of the inputs of the trigger 18 of the operating mode. Thus, in the Prepare mode, the mode trigger 19 is set to one. As a result, a logical 1 -c single output signal

five

0

five

the mode trigger 18 permits the passage of information from the control register 17 code to the control input of the multiplexer 3 through the AND 20 group of elements. At the same time, the address code of the cell into which information is to be entered is entered into counter 6 of address register 4. The contents of the counter 6 are fed to the address input of the on-line storage unit 7.1 and through the adders 11.1-11 (N-1) to the address inputs of the blocks of the RAM 7.2 - 7.N. In the Prepare mode for input buses 14.1–14 (N-1), the driver sends a combination of all zeros. Information that must be entered into the corresponding cell of one of the operative storage blocks 7.1-7.N with the address set in counter 6, from the register output 2 through demultiplexer 3 is fed to the input of one of the blocks 7.1 - 7.N. The number of the storage block in which the information is entered.

0

qi determines the control register 17 of block 1.

The operation mode starts when the trigger 18 of the operation mode of the control unit 1 is brought to the zero state. When this counter 6 starts to work in the counting mode (Fig. 1 of the starting circuit of the generator 5 clock pulses are not shown).

Blocks 7. 1 - 7.N start operation in the read mode.

The output code of the counter is fed to the address input of the block 7.1. The address inputs of blocks 7.2 to 7.N are fed to the codes from the outputs of the adders, 11.1-11 (N-1), which are the sum of the output code of the counter 6 and the control codes supplied to the corresponding inputs 14.1-14. (N-1 )

shaper. 5 I

In the formation of periodic

functions with a period T, the phase control of each function at the outputs of blocks 7.2 - 7.N can be performed

0 with discrete T / 2n, where n is the address code width, by changing the control codes supplied to the input 14.1-14 bus (N-1) of the driver.

5 Set of playable functions

can be changed, programmed accordingly. properly blocks 7.1 - 7.N. Phases of reproducible functions can be controlled continuously.

jerky in the process of device operation, and a certain code is skipped before the Operation in counter 6 mode, you can play a function with any initial phase corresponding to this code on the first channel (block 7.1) of the device.

If it is necessary to issue a function from one channel to another, the appropriate setup code is supplied to the control input 15 of the device. The setup code from the output of the register 13 is fed to the control inputs of the switch 8. On the corresponding depffreader of each of the multiplexers 8.1-8.N, the setup code is converted from positional to unitary, i.e. for each code, the decoder determines the desired output channel. The switch 8 reverses the output channels, depending on the setup code from the output of the setup register 13. This allows programs with a complex function in some channels to play them (or stop execution) on other channels. This mode of operation allows you to expand the field of application of the former, since any channel can work out the entire set of programs of complex functions.

Claims (1)

Invention Formula The former is a complex function that contains a clock generator, a register, addresses, a counter, a control unit, a first memory block, an information register, (N-1) adders, the address register output being connected to the counter information input, the counting input of which is connected to clock output, input 87135 -4 controlling the operation mode of the counter is connected to the first output of the control unit, the output of the counter is connected to the address input of the first operational memory block and to the first information inputs (N-1) of adders, the second information inputs of which are connected to (N-1) information inputs Former, respectively, about the fact that, in order to expand the functionality by reconfiguring the output channels of a complex function, (N-1) operational section blocks, a demultiplexer, a setup register, a switch, moreover, the output of the i-oro adder (i 1 - N - 1) is connected to the address input i-nd of the 1st memory block, the output of the K-th. 20 (, N). the operating memory unit is connected to the K th information input of the switch, the control input of which is connected to the output of the setup register, whose information input is connected to the setup input of the former, the second output of the control unit is connected to the control input of the demultiplexer, whose information input is connected to the output the register 30 information output of the demultiplexer is connected to the information inputs of the RAM blocks, quiches of the switch are connected to the information outputs of the driver, respectively, the control unit contains a control register, a mode trigger, two groups of I elements, and a forward mode trigger output is connected to the first inputs of the elements And the first group, the second inputs of which are connected to the outputs of the higher bits of the control register, the outputs of the lower bits of which are connected to the direct inputs of the elements And second 45 groups, the second inputs of which are connected to the Inv, the trigger output of the mode. fie, 2