SU1247871A1 - Microprogram control device with self-check - Google Patents

Abstract

The invention relates to the field of automation and computing. The purpose of the invention is to increase the reliability of the control. The goal is achieved by providing periodic self-monitoring of the microprogram control device during the execution of the work program. we. The device contains an address generation unit, an address counter, a microinstructions memory block, a data register, a decryption block, a modulo-two block, a trigger, and AND NOT AND OR elements. The device allows the execution of the work program contained in the microinstructions memory block, as well as the monitoring of microinstructions and the translation addresses of the microinstructions memory block. teams. 2 Il. to oo

Description

The invention relates to computing, in particular to firmware control devices.

The purpose of the invention is. increase the reliability of control.

FIG. 1 is a block diagram of a self-monitoring microprogram control device; Fig. 2 is a block diagram of the multiplexer of the address generation unit.

The microprogram control unit with self-control contains an address 1 generating unit consisting of adder 2 and multiplexer 3, an address counter 4, a microinstruction memory 5, a microinstruction register 6, a decryption block 7, a convolution node modulo two 8, a trigger 9, and elements - NOT 10, elements. And 11 n 12, element OR 13, elements AND 14 and 15, information inputs, information outputs 17, start input 18, work mode input input 19, synchronization input 20.

The multiplexer (figure 2) contains

element NOT serving to effect information.

The address counter 4 is a binary counter with parallel

5 by transfer, with chains of parallel reception of information for setting the initial value of the counter and resetting. The address counter detects a transfer signal during the transition from the state of all units to zero at the overflow output. The recording and counting in the address counter is carried out by a difference from one to zero with the corresponding recording and counting signals.

f5 The microinstructions memory unit 5 is intended for storing microinstructions and is a read only memory in which, when called ONE address, one specific information corresponding to this address is always read.

The microinstructions register 6 is a parallel binary register for receiving, storing and transmitting information 21, elements AND 22 ,,.,., 22 5 of information. Execution on the D-trig (where n is the value of the address field of the register of micro-operations) is the element OR 23, the element is NOT 24.

The address forming unit 1 is designed to form the address of microscopes with a natural order, the addresses of microcommands of conditional jumps, as well as to generate control signals by writing and addressing the address,

The adder 2 of the address forming unit 1 is a parallel binary adder that performs the operation of summing binary numbers. The adder is made on the basis of single-bit combinational adders built on the AND, OR, and RUNTIME OR elements. The adder can also be made on the basis of single-digit combinational adders and an accelerated intergroup transfer scheme.

The multiplexer 3 of the address addressing unit 1 is designed to receive information on one of the information 50 inputs, depending on the control signals from the output field of setting the code of logical conditions of the register of microcommands and transmitting it to the direct and

Herah with a combined sync input. The reception of information into the register is carried out by a difference from one to zero on the synchronizing input. The microinstructions register also contains the zero setting scheme.

The decryption unit 7 is designed to form microoperations by means of desfraction and is. 32 block decoders with combined

sync inputs.

The modulo two 8 convolution node is a functional node that performs the modulo addition function of two multi-bit binary code. In this node 8, a parity check is performed on a multi-bit binary code with a check bit value.

The check for parity is performed according to the expression

40

45

f, P x; @ Xj @. . .x,. @ - 1 © x. ® x „® X,,

where X (ie1, m) is the i-ro value of the binary code; X - the value of the control

bit Convolution node modulo two 8 inversion device outputs. In the composition- 55 is filled on the elements EXCLUSIVE OR

The multiplexer has a built-in decoder circuit that decrypts the control signals, and

element NOT serving to effect information.

The address counter 4 is a binary counter with parallel

transfer, with chains of parallel reception of information for setting the initial value of the counter and resetting. The address counter detects a transfer signal during the transition from one to zero state at the output of the overflow. The recording and counting in the address counter is carried out by a difference from one to zero with the corresponding recording and counting signals.

The microinstructions memory block 5 is designed to store microinstructions and is a permanent storage device, in which when calling ONE address, one specific information is always read corresponding to this address.

The microinstructions register 6 is a parallel binary register used to receive, store and transmit information. Run on D-Trig

Herah with a combined sync input. The reception of information into the register is carried out by a difference from one to zero on the synchronizing input. The microinstructions register also contains the zero setting scheme.

The decryption unit 7 is designed to form microoperations by means of desfraction and is. block decoders with combined

sync inputs.

The modulo two 8 convolution node is a functional node that performs the modulo addition function of two multi-bit binary code. In this node 8, a parity check is performed on a multi-bit binary code with a check bit value.

The check for parity is performed according to the expression

f, P x; @ Xj @. . .x,. @ - 1 © x. ® x „® X,,

where X (ie1, m) is the i-ro value of the binary code; X - the value of the control

bit Convolution node modulo two 8 convolutions of the pyramidal scheme. Trigger 9 is asynchronous.

RS trigger.

l12

The multiprogrammed control device with self-control works in the following modes: in the operating mode, when the device is occupied by executing the working program read from the microinstructions memory block, with the development of microoperations at the information outputs of the device; in the control mode, when the device is occupied by checking the microcommands of the microcommand memory block and the jump addresses by condition.

. In the initial state of the device, trigger 9 is in the zero state, in the counter of address 4 the code zero is stored and in the register of micro-instructions the code of the previous micro-command.

The operating mode of the self-monitoring microprogram control device is characterized by the fact that the trigger 9 is in the zero state. In this mode, the high potential of the zero output of the trigger 9 permits the passage through the AND 12 element of the sync pulse of the synchronization input 20 to the synchronization input of the decryption unit. Thus, at the information outputs of the device 17, respectively, with a sequence of sync pulses of the synchronization input, a sequence of micro-operations is generated. The low level of the single output of the trigger 9 is independent of the state from the output of the convolution node modulo two 8 and the inputs of the operation mode setting 19 forms a high potential at the output of the AND-NE element 10 allowing the sync pulses from the sync input 20 to exit through the sync pulse 20 20, passing through the element 11, enters the synchronization input of the register of microcommands 6 and records the microcommands 6 from the outputs of the memory module of microcommands 5 into the register of microcommands 6, the post falls to the inputs of the elements 14 and 15 and from the output values of the multiplexer 3, the address generation unit 1 records or counts the address in the address counter 4. The outputs of the multiplexer 3 address generation unit 1, depending on the information from the setting field of the logical conditions register of the microinstruction 6, are transmitted from information signals 16 coming from the control object. If the outputs are multiplex714

Since block 3 of the address forming unit 1 is transmitted a high level control object signal, then the high potential level of the direct output of multiplexer 3 of the address formation block 1 and the low level potential of the unit output of the trigger 9 through the Rrni 13 element allow the passage of the sync pulse from the And 11 element output through And 14 element to the counting input of the address slit 4, increasing its contents by one, and the low potential level of the inverse output of multiplexer 3 of the block forming address 1 and the high level potential of the zero output trigger 9 but prohibits passage of clock output from the AND gate 11 through the AND gate 15 to the account record entry, address 4 snip.

If the signal of the low-level control object is transmitted to the outputs of multiplexer 3 of the address-forming unit 1, then the low-level potential of the direct multiplex output) and 3 units of the formation of the address 1 and the low-level potential of the single output of the trigger 9 through the OR 13 11 through the element 14 on the counting input of the counter of address 4, and the potential of the high level of the inverse output of multiplexer 3 and the potential of the high level of the zero output of the trigger 9 allow the passage of a sync pulse from the output of the element 11 through the element 15 to the input of the record of the address counter 4, recorded the code of the transition address in the counter of address 4 formed at the outputs of the adder 2 of the block forming the address 1, determined by the sum of the codes of the contents of the address counter 4 and the code field of the address of microinstruction registers 6,

At the generated address stored in the address 4 counter, the microcommand is read from the microcommand memory block. 5. The following sync pulse from the output of the And 11 element records the microcommand of the microcommand memory block 5 into the microcommand register 6 and changes the contents of the address counter 4 depending on the code of the microcommand register address field 6 and the corresponding value of the signal of the control object.

The signal at the start input 18 performs the installation in the unit

trigger 9, setting the zero of the address counter 4 and the microinstructions register 6, and places the microprogrammed control device with self-control into the control mode of operation.

Low level of zero output of trigger 9 prohibits the passage of a sync pulse from sync input 20 through element 12 to the synchronization input of decryption unit 7 and the passage of a sync pulse from element 11 output through element 15 to input of a record of address counter 4. High potential of single output of trigger 9 regardless of the output value of multiplexer 3 of the address forming unit 1 through the element OR 13, allows the output pulse of the AND 11 element to pass through the AND 14 element to the counting input of the address counter 4. High input potential setting the operation mode 19 and the high potential of the single output of the trigger 9 forms, at the output of the NE-10 element, a state dependent on the output value of the node 8 Low output of the convolution node modulo two 8, indicating that there is no scan error through the element AND-NOT 10 allows the synchronization input of the synchronization input 20 to pass through the element 11 that enters the synchronization input of the microinstructions register b and through the element 14 to the counting input of the address counter 4 and records the microcommand of the microinstruction memory 5 microinstructions 6 and an increment by unit of the contents of the address counter 4, the generated microcommand codes of the microcommands register 6 and the total address code contained in the address counter 4, and the address code field of the microcommands register 6 are fed to a group of inputs of the convolution node modulo two 8 in which The parity check of the microinstruction and the transition address is carried out. The high output level of the modulo two 8 knot, indicating the presence of a parity error, through the NAND element 10 prohibits the passage of a sync pulse from the synchronization input 20 through the element 11 11 and suspends the operation of the microprogram control device with self-control.

If there is no parity error of the microcommand and the address of the transition at the output of the convolution node modulo two 8, a low potential is constantly present, which allows the next sync pulse from the synchronization input 20 through the AND 11 element entering the microcommand register input through the AND-10 elements. 6 and to the counting input of the address counter 4, and thereby writes the next microcommand from the outputs of the microcommand memory block 5 to the microcommand register and increments the content of the address counter 4 by one. The sync pulses from the output of the And 11 element repeat in this case the actions on reading the microinstructions from the microinstructions memory block 5 V. The register of microinstructions 6 and increasing the contents of the address counter 4 until the overflow signal of the address counter 4 that sets the trigger zero to 9 and transferring the self-monitoring microprogram control device to the operation mode.

If you wish to perform a scan without stopping and if there is an error in the microcommand or an error in the transition addresses, applying a low potential at the input of operation mode setting 19, regardless of the state of the single output of the trigger 9 from the output of the convolution node modulo two 8, the output element AND-NOT 10 high potential, allowing passage through, the element 11 of the sync pulse of the synchronization input 20. The sync pulse of the output of the element 11 is fed to the sync input of the microinstruction register 6 and, through the element 14, on An electronic input of the counter of address 4 records microcommands from the output of the microinstructions memory block 5 to the register of microinstructions 6 and the increment of the contents of the address counter 4 by one. The subsequent output and element sync pulses of element 11 repeat readout operations from .miiKpoKOMa the memory of micro-instructions 5 to the register of micro-instructions 6 and the increase in the contents of the address counter 4 until the occurrence of the signal of the full counter of the address counter 4, which sets the zero of the trigger 9 and transfers the microprogram control device with self-control to Chii mode. Thus, the self-monitoring firmware program executes the work program contained in the memory of the micro-instructions 5; control of microinstructions and addresses, transition of the memory of microinstructions 5 and adder 2 of the block of formation of addresses 19 of the counter of address 4 and data register 6.

Claims (1)

Invention Formula A microprocessor with self-control, containing an address generation unit, a decryption unit, a trigger, an OR element, the first, second, third and fourth AND elements, a micro-command register, a micro-command memory block, and an address counter, and the micro-command memory output outputs are connected to information inputs register of microinstructions, the synchronization input of the device is connected to the first input of the first element AND, characterized in that, in order to increase the validity of the control, it contains an AND-NOT element, a module of convolution two, and a block forming the address contains an adder and a multiplexer, with the device synchronization input connected to the first input of the second element And, the output of the first element And connected to the input of the register of microcommands, the first inputs of the third and; the fourth AND element, the second input of the third AND element is connected to the output of the OR element, the first input of which is connected to the forward output of the multiplexer, the inverse output of which is connected to the second input of the fourth AND element, the output of which is connected to the input of the address counter, group informational inputs of which are connected to the group of outputs of the adder and the first group of informational inputs of the convolution node modulo two, the output of which is connected to the first input of the NAND element, the second input of which is connected to the direct output of the trigger and the second input of the OR element, the output of the NAND element. connected to the second input of the first element And, the inverse output of the trigger is connected to the second input of the second element And the third input of the fourth element And, the output of the second element And connected to the synchronization input of the decryption unit, the outputs of which are information outputs the device, the start input of which is connected to a single trigger input, to the reset input of the microinstructions register and the reset input of the address counter, the sum- | The measuring input of which is connected to the output of the third element I, the group of bit outputs of the address counter is connected to the group of address inputs of the microcommand memory block and the first group of information inputs of the adder, the second group of information inputs of which is connected to the group of outputs of the microcontrol register address and the second group of information inputs of the convolution node by module two, the output of the overflow of the counter of the address is connected to the zero input of the trigger., - group of outputs, the field of setting the code of logical conditions of the microinstructions register is connected to the group the control inputs of the multiplexer and with the third group of information inputs of the convolution node modulo two, the fourth group of information inputs of which are connected to the group of outputs of the register micro-operations floor microinstructions and with the group of information inputs of the decryption unit, the synchronization input of the modulo two convolution node is connected to the output of the microcommand register control feature, the third input of the NAND element is connected to the input of the device operation mode, the information inputs of the multiplexer are connected to the information inputs devices. Pt / e.7 From IS / J pr my exit - HHSfpc- Hb / uSbf- xod OmSfl-S a 21 Compiled by A. Sirotska Editor I. Segl nik Tehred E. Chitkmar Proofreader O. Lugova Order 4127/49 Circulation 671 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, st. Project, 4 0ei, 2