SU1243106A1 - Controlled generator of pulse sequences - Google Patents

Abstract

The invention can be used in systems of digital processing and transmission of information, dp test control of logic blocks of computer technology. The purpose of the invention is the expansion of functionality. The device contains a reference frequency generator 1, an AND 5 element and a shift register 8. Introduction to the device of counters 2 and 3 with a variable division factor, a shaper of 4 pulses based on the decline of the front of the input signal, a shaper of 7 short. pulses on the front of the input signal and the shift register 9 allows alternately forming pulse sequences of a given structure. pry with a variable number of information bits and a wide range of adjustment of the period of the pulse. 1 il. t .. 4 CO

Description

I

1243

The invention relates to a pulse technique and can be used in systems of digital processing and transmission of information, test logic control of logic blocks of computer technology.

The aim of the invention is to extend the functionality by alternately forming pulse sequences of a given structure with a variable number of information bits and a wide range of control over the pulse following period.

On the drawing there is a flow chart of the controlled generator of pulse sequences,

The controlled pulse pulse train contains a reference frequency generator 1, counters 2 and 3 with a variable division factor, a driver 4 pulses on the front edge of the input signal, element 5, a delay line 6, a driver 7 short pulses on the front of the input signal, shifting registers 8 and 9. bus 10 launch

bus 11, the output of the device, the output of the generator 1 of the reference frequency is connected to the counting input of the first counter 2 with a variable division factor, the output of which is connected to the driver 4 pulses on the falling edge of the input signal, § the output of the driver 4 pulses connected to the first input of the And 5 element and with the counting input of the counter 3 with a variable division factor, the output of which is connected to the second input of the element 5 and to the input of the imager 7 short pulses on the front of the input signal, the input of the element 5 is connected to the input of the line 6. back Holders whose output is connected to the shift shift register input 8, the drive of the short pulse generator 7 is connected to the record input information and in the parallel shift register code 8, the bus 11 of which is the output of the shift register outputs 9 to the counter 2 inputs with a variable division factor, W whose outputs are connected to the corresponding inputs of setting the division factor of counter 3 with a variable coefficient

five

five

0

1061.

dividing unit, and bus 10 serves to set the initial conditions.

The controlled pulse sequence generator operates as follows.

The pulses from the reference frequency generator 1 are fed to the counting input of the counter 2 with a variable division factor. In the initial state, the division factor of the counter 2 ,. set by the shift register 9 is equal to zero, and the frequency at the output of counter 2 is zero.

Information on the bus 10 about the required period of the pulses and the number of pulses in the bundle arrives at the shift register 9 and sets the initial conditions in the corresponding bits 1.. .g, 1. . . shift register 9. In this way, the pulse period is controlled with a multiplicity corresponding to a period of only a pulse of the reference frequency generator 1, and each combination of symbols recorded in register 9 cells corresponds to a certain frequency at the output of counter 2. Pulse frequency j-btxHa output of counter 2 with a variable division factor when 1 pulses are fed to the counting input from the reference frequency generator 1 is determined by the formula

g M -4-wow

where -fbX is the reference oscillator frequency

frequencies

P - the number of bits of installation of the division factor; H is the division factor,

M V2l. . 2 L, „+ Ug. .i

where Vi is the bit number of the installation. Shaper 4 pulses on the decay of the front of the input signal, pulses are rigidly tied to the trailing edge of the pulses coming from counter 2 with a variable division factor. The pulses from the output of the imager 4 are fed to the input of the counter 3 with a variable division factor. Each combination of nfi cc-gmvol 5 recorded in the shifting cells, its register 9, corresponds to a certain duration of the string at the output of the counter 3, which through the element I is filled with pulses from the shaping device 4, and formed into a packet of pulses, the number of which is determined by the duration the strobe enters through the delay input line 6 of the shift-register 8 as shift pulses. To write parallel binary information (xt-j of a given structure, a pulse formed from a strobe arriving at shorter pulses 7 on the front of the input signal arrives at the input of writing a parallel shift register code 8. With the arrival of a packet of shift pulses from the register 11 bus 11, a pulse sequence is output of a given structure with a variable number of information bits and a wide range of control over the period of following pulses in a pack

Claims (1)

Invention Formula A controlled pulse sequence generator containing a reference frequency generator, an And element and a first shift register, characterized in that, in order to extend the functionality, the first And second counters with L.Gratillo editor are additionally introduced into it Compiled by R.Matveeva Tehred N. Bonkalo Proofreader G. Reshetnik Order 3717/56. Circulation 816 VNIRPZH USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, 4/5 Raushsk nab. Production and printing enterprise, Uzhgorod, st. Project, 4 2431064. belt division factor, pulse shaper on the decay, front of the input signal, driver of short pulses on the front of the input 5 signal, delay line and the second shift register, and the input of the first counter with a variable division factor is connected to the output of the reference frequency generator, output of the 10 torcator the decay of the front of the input signal is connected to the first input element And the input of the second counter with a variable coefficient division, the output of which is connected to the 15th second input of the AND, .I. the outputs of the first shift register are connected to the corresponding inputs of the installation of the division factor of the first counter with a variable division factor of 20, and the hi outputs are connected to the corresponding inputs of the installation of the division factor of the second counter with a variable division factor; the input of the delay line is connected to the output of the AND element , the input of the short pulse generator on the front of the input signal is connected to the output of the second counter with a variable division factor, the input of the information recording of the 2Q of the second shift p The register is connected to the output of the short pulse generator on the front of the input signal, and the shift input is connected to the output of the delay line. Subscription