SU1233292A1 - Synchronizing device - Google Patents

Abstract

The invention relates to radio engineering and provides a reduction in the time of entry into synchronism and increase noise immunity. The phase detector 1 receives an input signal and a signal of a controlled reference oscillator (UOG) 4. The voltage of the beats from the phase detector 1 is fed to the cooler 2, and through the differentiating unit 5 to the driver 6 of the counting direction signals. Using pulse counting signal generator 6, the pulses allocated by differentiating unit 5 are separated and fed to the corresponding inputs of the reversible counter (PC) 7. The PC 7 state is converted by the DAC 8 and fed to another input of the adder 2. The voltage from the adder 2 through The LPF 3 is fed to the VOG 4 to control its frequency and phase. The voltage from the adder 2 is also fed to the controlled band-pass filter 9 with variable attenuation. This filter turns off the constant transient and modulating function of the transient function. The voltage from its output through the A / D converter 10 enters the form of the initial frequency detuning to PC 7. At the time of changing the value of PC 7, the UOG 4 control voltage changes abruptly. provide clock operation of the device blocks. 2 Il. i (L yu: lAd tsD UD tc Lee. / Sf. blue ft.

Description

The invention relates to radio engineering and can be used in

asynchronous address transfer systems and radio navigation systems for reference oscillation.

The purpose of the invention is to reduce the time to synchronization and increase noise immunity.

FIG. Figure 1 shows the electrical circuit diagram of the synchronization device; in fig. 2 - time-diagrams of signals, explaining the operation of the synchronization device.

The synchronization device contains a phase detector 1, cyr-tMaTop 2, a filter of 3 nuc frequencies, a controlled reference oscillator 4, a differentiating unit 5, a shaper of counting signals, a reversible counter 7, a digital-analogue converter 8, a controlled band-pass filter 9 s variable attenuation, analog-to-digital converter 10, clock oscillator It, driver 12 blocking pulses, driver 13 trigger pulses, delay line 14.

The synchronization device works as follows

The input of the synchronization device (Fig. 1) receives the input signal S (t) A (t) cos cOpt-HC () (t), where A (t) is the envelope; F (t) is the phase increment; MO is the frequency of the reference oscillation.

The controlled reference generator 4 is generally upset by the frequency uW tto-Qg, where cOfj is the frequency of the controlled reference generator 4 at the initial moment of time. It will be determined in the ground state of the reversible counter 7 corresponding to the phase error. Therefore, a beat voltage appears at the output of phase detector 1: (Fig. 2a). The fronts of this voltage, corresponding to the reverse section of the quasi-peak-like characteristic of the phase detector 1, are detected by means of the differentiating unit 5. The pulses at the output of the differentiating unit 5 can be either negative or positive.

With the help of a shaper 6, which can be made as a detector with the appropriate inverting and amplification of voltage (power), the pulses are separated and sent 2332922

The input of the direct count input and the countdown input of the reversible counter 7 are respectively input. The state of the reversing counter 7 of the digital 5 form is converted into analog form using the diffro-analog converter 8 (Figure 26). This voltage is summed in the adder 2 with the output the voltage of the phase detector 0, the controller 1, controls the frequency and phase of the refillable reference oscillator 4. The signal at the output of the adder 2 is shown in FIG. 2c. Data signal up to mo

time t is monotonous. A similar waveform is valid only for a modulated reference oscillation. when the phase modulation index of the input signal is much less than one,

The 3 NIL filter band is designed to smooth the signal at the output of the Cz mmator 2, which may be non-monotonic due to the formation of a discrete voltage. the difference is insignificant, and the time constant of the low-pass filter 3 can be chosen much shorter than the time constant of the synchronization device. Therefore, by its characteristics, the synchronization device approaches the first-order phase-locked-frequency systems.

In the case of an input modulated signal, the voltage at the output of the adder 2. as well as at the input of the controlled reference oscillator 4, in the presence of frequency detuning, has the form

l / {i) (). 5

fA

Ichmaks I

xCoS (51it + tf;)

 ;

and, accordingly, the partial indices of the phase modulation, the frequency of the spectral components and the initial phases;

constant component of the control voltage;

TA

d 't is the time constant of the phase-locked loop frequency, the steepness of the characteristic of the phase detector 1;

initial frequency layout;

retention band.

Thus, in the transient synchronization device, the transient function is combined additively with the modulating function. This proposed synchronization device, which is basically a linearized phase-locked loop (PLL) system, is significantly different from conventional non-linear PLL systems, where

These two processes multiplicatively pass through a nonlinear element — a phase detector, with the result that their spectra are so intermixed that the functions cannot be separated.

Thus, in the proposed synchronization device, the function of the transition process (the second term) of the form, carrying information about the initial frequency detuning, exists independently of the modulating function.

The voltage from the output of the adder 2 is fed to the information input of the controlled band-pass filter 9, which filters both the constant component U and the modulating function from the transient function, by which in general can be implied random effects (noise). The type of signal at the output of the controlled band-pass filter 9 is shown in Fig. 2d (curves I, II, III). These three signal values differ from each other in different values of the initial one with a frequency offset of 4 co.

The synchronization device, in the process of eliminating the initial frequency error, is synchronized by the clock generator 11, which operates in the auto-oscillatory mode and generates rectangular pulses of small duty cycle (Fig. 2d).

The operation of the clock generator 11, therefore, the entire device.

292

synchronization can be synchronized by an external source, the signal of which must be fed to the input of the clock generator 11. The falling edge of the pulse of the clock generator 11 starts the drivers 13 and 12, the output signals of which are shown respectively in FIG. 2 e and 2.

Shaper output

13 enters the analog-to-digital converter 10, fixing its state, as well as through the delay line 14 (Fig. 2h) the recording resolution input of the reversible counter 7 ,. At. In this case, the signal from the outputs of the analog-digital converter 10, whose state in digital form corresponds to the initial frequency detuning of the first, is written to the reversible counter 7 and the output of the digital-to-analog converter 8, and hence to the adder 2, is generated at time tj. voltage jump, as a result of which the frequency of the controlled reference oscillator 4 becomes equal to the carrier frequency of the input signal.

In order that the voltage jump at the output of the adder 2 does not cause transients in the controlled bandpass filter 9, and hence the false triggering of the analog-to-digital converter 10, the damping of the controlled band-pass filter 9 (after fixing the state of the analog-digital converter 10 ) increases dramatically by applying a signal from the output of the generator 12 to the control input of the controlled band-pass filter 9. In the latter, circuits containing capacitors are short-circuited, and circuits containing inductances are opened, due to h its attenuation of the controlled bandpass filter increases dramatically, and the signal at its output becomes zero (Fig. 2a).

Claims (1)

Invention Formula A synchronization device containing a series-connected adder, a low-pass filter, a controlled reference oscillator and a phase detector, a series-connected reversible counter and a digital-to-analog converter, the output of which connected to the first input of the adder, as well as the differential 4) the differentiating unit and the delay line, the information input of the phase detector being the device input, characterized in that, in order to reduce the synchronization time and more noise immunity, serially connected clock generator, blocking pulse driver, controlled band-pass filter variable attenuation and analog-to-digital converter, as well as the driver of the counting direction signals and the driver of trigger pulses, while the additional output of the clock generator through the driver of trigger pulses and the delay line They are connected to the input of the resolution of the reverse counter meter, whose information inputs are connected to the corresponding outputs of the analog-digital converter, the control input of which is connected to the output of the trigger pulse former, the output of the phase detector is connected directly to the second input of the adder and through the differentiating unit — to the input of the counting signal generator, the first and second outputs of which are connected respectively to the direct count input. and the reverse count input of the reversible counter, and the output of the adder is connected to the information input of the controlled band-pass filter with variable attenuation. Editor A. Sabo Compiled by V. Orlov Tehred O. Gortzai Order 2784/58 Circulation 624 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Ra: / shska nab., d, 4/5 Production and printing company, Uzhgorod, st. Project, 4 Proofreader S. Shekmar