SU1213542A1 - Tuneable pulse repetition frequency divider - Google Patents

Abstract

The invention relates to a pulse technique and can be used in pulse phase locked loop systems, for example, in frequency synthesizers and time slots. The purpose of the invention is to expand the functionality by providing half-integer values of the division factors while simultaneously increasing the uniformity of the input pulses. The device contains a pulse counter 1 having i-bits, the first 2 and second 6 triggers, the first 4 and second 11 inverters, the control bus 5 and the output bus 7, the first 8 and second 9 elements EXCLUSIVE OR, the division factor 10 bus and input bus 12. Pulse counter 1 is made subtractive, with the possibility of pre-installation. It can be binary or binary-decimal. 3 il. (L'e cond) 4 1C Fmg.1

Description

I

The invention relates to a pulse technique and can be used in a pulse phase locked loop system, such as frequency synthesizers and time slots.

The purpose of the invention is to expand the functionality of the device by providing half-integer values of the division factors, while simultaneously increasing the uniformity of the output pulses. .

Fig. 1 shows an electrical structural diagram of a tunable pulse divider; in fig. 2 and 3 are timing diagrams explaining the operation of the device in various modes.

The tunable pulse frequency divider contains a pulse counter 1, which has AND bits, the first trigger 2, the element OR 3, the first inverter 4, the input of which is connected to the control bus 5, the second trigger 6, the p input of which is connected with a common thickness, S- input with the output of the element OR 3, inverse output with the output bus 7, with the input of the presetting of the pulse counter 1 and with the C input of the first trigger 1, the direct output of which is connected to the first input of the first element EXCLUSIVE OR 8, R - input.- with the input of the first inverter 4 output which о is connected to the first input of the second element EXCLUSIVE OR 9, the second, the input of which is connected to the output of the first (the least significant | bit of counter 1 pulses, the output to the first input of the element OR 3, the inputs from the second to the h -th of which are connected The pulses of pulse counter 1, whose information inputs are connected to the corresponding bits of the bus 10 of the division coefficient code, subtracts (counting) input through the second inverter 11 to the C input of the second trigger 6 and directly from the (e -1) th input of the OR 3 element and with the release of the first email EXCLUSIVE OR 8, the second input of which is connected to the input bus .12.

Pulse counter 1 is subtractive with pre-installation capability. It can be binary or binary-decimal.

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The device works as follows.

With a total dividing factor, for example, equal to 3, into a bus 10

5, the binary code of the number 3 is supplied, and the bus 5 receives the logical O. A signal is sent to the bus 12 - a continuous sequence of pulses with a duty cycle of two (Fig. 2a).

 About the input of the element 8, the trigger 2 constantly maintains the logic level O (Fig. 2k), and the signal from the bus 12 passes to the subtractive input of the counter 1, without changing the phase (Fig. 2b.

15 Each positive differential signal on the subtractive input of counter 1 reduces its content by one (Fig. 2). When counter 1 reaches the state O - 01, taking into account 20 that the signal from the output of the first bit (Fig. 26} is inverted by element 9, since logical 1 is present at the second input of element 9 (Fig. 2), to all inputs of element 3 A logical O is applied, and a negative pulse appears at the output of element 3 (Fig. 2de), which sets the trigger 6 to one state. On bus 7, an impulse appears

30 (.fig.2ts /, the duration of which

equal to the period of the input signal. At the same time, this impulse arrives at the presetting input of counter 1 and rewrites the number 3 into it from the bus 10.

Further, the operation of the device is repeated. Thus, the trigger 6 forms at the device output a sequence of pulses, the duration of which is equal to the period

the input signal, and the following frequency is three times less than ours 12.

With a half-integer division factor, for example, equal to 3.5, per bus

45 10 the binary code of the number 3 is supplied, and the bus 5 is logically 1. On the bus 12, a signal comes up - uninterrupted. The sequence of pulses is equal to two (Fig. 3A), Trigger 2

50 is in zero state

(fig.ZK), and the input signal; through the element 8 is fed to the subtracting input of the counter 1, without changing the phase (fig.Z. Each positive

55, the differential signal at the input of counter 1 reduces its content by one (fig.Zr.d). The signal from the output i of the first discharge of counter 1 (Fig.Zv)

35

passes through the element 9 is not izmeshpg phase (fig.Ze), since at its first output there is always a logical O (fig.Zo). Therefore, a negative pulse at the output of element 3 (Fig. Zh. Appears after the counter 1 has reached the state O - 00. This corresponds to an increase in the division factor by one, i.e. the division ratio as it became 4.

The pulse from the output of element 3 sets in one state trigger 6. On bus 7, an output pulse is formed (Fig. 3i), the duration of which is equal to the period of the input signal. The output pulse of the device again writes the code of the number 3 to the counter 1 and changes the state of the trigger 2 to the opposite one (Fig. 3k).

During the next cycle of operation, the signal to the subtracting input of counter 1 is supplied in antiphase compared to the signal on bus 12 (FIG. 10–). Since the counter 1 always switches by a positive differential of its input signal, this cycle of de / 1eni and each subsequent one begin on half

a period earlier (Fig. 3), which corresponds to a decrease in the division factor by 0.5. On bus 7, a uniform sequence of pulses appears (Fig. 3, duration

which is equal to the period of the input signal, and the follow frequency is 3.5 times less than the input frequency.

  .-.

Claims (1)

Invention Formula A tunable pulse frequency divider containing 135424 a pulse counter having R bits, a first trigger, an OR element, an input and V-bus, a dividing ratio code bus, and a first inverter 5, whose input is connected to a control bus, characterized in that, in order to expand the functional possibilities by ensuring the half-integer values of the division factors while simultaneously increasing the uniformity of the output pulses, a second inverter, two EXCLUSIVE OR elements and a second 15 trigger, D - the input of which is connected to the common bus, S -input - to the output of the element OR, the inverse output - to the output bus, with the input of the pulse counter presetting and with the output of the first trigger, the direct output of which is connected to the first input of the first element EXCLUSIVE OR, R the input to the input. the first inverter, the output of which is connected to the first input of the second element EXCLUSIVE OR, the second. the input of which is connected to the output of the first discharge of the pulse counter, the output to the first input of the element | OR inputs from the second through h - and which are connected to the outputs of the corresponding bits of the pulse counter, the information inputs of which are connected to the corresponding bits of the bus of the division factor code, the subtracting input through the second inverter to the C input of the second trigger and directly to the (+ Om input of the OR element and to the output of the first EXCLUSIVE OR, the second input of which is connected to the input bus. J JlJTJ J Jt to 2. F14, d Compiled by A.Sokolov Editor O. Golovach Tehred Z.Kastelevich Proofreader M.Demchik 786/61 Circulation 813 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035 Moscow Zh-35 Raushsk nab., Branch ShSh Patent, Uzhgorod, Proektna St., 4