SU1145477A1 - Reversible counter - Google Patents

Abstract

A REVERSIBLE COUNTER containing a bus bus, two control buses of the recalculation mode and n bits, each of which contains an AND-OR element and a 0-flip-flop that has inputs of an asynchronous installation, the clock and information inputs of which are connected respectively to the input bus and the output of the AND element -Sh1I, the first inputs of the first and second structures AND of which are connected respectively to the direct outputs of the D triggers of the previous one and the next ones into bits, the second input of the first structure P of the AND-OR element of the first bit is connected to the second inputs of the first structures AND elements AND-OR of the remaining bits, the second inputs of the second structures AND elements AND-OR are connected to the second input of the second structure AND element AND-OR of the first bit, which is due to the fact that, in order to expand the functionality by providing reversible single codes of recalculation, two installation buses are entered into it, two AND elements, two OR-NOT elements, an NOT element, and - each digit except the first and last - an addition element modulo two and the majority element, for the first time d introduced the element of addition by m odule two, the first control of the conversion mode is connected to the first inputs of the first and second elements AND whose outputs are connected respectively to the first inputs of the first and second elements OR NOT, the second inputs of which are connected respectively to the first and second installation buses, the outputs of the first and second elements OR-NOT are connected respectively to the third inputs of the second and first elements of W1N-NOT and the second inputs of the first and second structures AND the AND-OR element of the first bit, (L the second inputs of the first and second elements AND Inen respectively: with the direct outputs of the O-flip-flops on; the last and the first bits, in each category, except the last, the first and second inputs of the element are combined and modulo two are connected respectively to the direct output of the D-trigger and the second bus control mode ne4: recalculation, which is connected to the input sl of the element NOT, in each discharge, except the first, the output of the addition element modulo two is connected to the first input of the majority element, the second input of which is connected to the output of the element NOT, and the third input of the majority each item The second bit, except the second one, is connected to the output of the major element of the previous bit, the third input of the majority element of the second bit is connected to the output of the addition element modulo two of the first bit.

Description

The invention relates to discrete automation and computing technology and can be used as a multiprogrammed reversible counter of a single code and distribution of level bodies. Known reversible counter containing a Johnson reversible counter with D-triggers and I-SHSh-N elements, two AND elements, two AND-NOT elements, two AND-OR elements, AND-OR-NOT element clock bus, as well as an installation and task bus recalculation mode til The disadvantage of this device is limited functionality, since it is impossible to both bake the formation modes of reversible unit codes. A reverse counter is known that contains an input bus, two control buses in a conversion mode and AND bits, each of which contains an AND-OR element and a D-trigger that has inputs of an asynchronous installation, the clock and information inputs of which are connected respectively to the input bus and the output of the element AND-OR, the first inputs of the first and second structures AND of which are connected respectively to the direct outputs of the D-triggers of the previous one and the next one in the ring of bits, the second one of the first structure of the AND-OR element of the first bit is connected to the first pin different control of the recalculation mode and the second inputs of the first structures AND AND-OR elements of the remaining bits, the second inputs of the second structures AND elements. Combo AND-OR which are connected to the second input of the second structure AND element I-IL of the first discharge and the second control of the recalculation mode 2}. A disadvantage of the known device is its limited functionality, since it will provide a mode of circular recording, ha pre-recorded in one: from bits of the unit and it is impossible nor I to get reverse single conversion codes. The purpose of the invention is to enhance the functionality by providing reverse unit cds of recalculation. To achieve this goal in a reversible counter. Contains input bus, two control buses for counting and n bits, Each of which contains an AND-OR element and a D-trigger that has inputs of an asynchronous installation, the clock and information inputs of which are connected respectively to the input bus and the output of the AND-OR element, the first inputs of the first and second structures AND of which are connected respectively to the direct outputs of the D-triggers of the previous and subsequent in the ring of bits the second input of the first structure AND of the AND-OR element of the first discharge is connected to the second inputs of the first structures AND a ntov AND-OR of the remaining bits, the second inputs of the second structures AND elements AND-OR which are connected to the second input of the second structure AND element AND-OR first discharge, introduced two installation buses, two AND elements, two OR-NOT elements, NOT element , and in each category, except the first and last, there is an addition element modulo two and a majoritarian element. In the first discharge, an addition element is introduced modulo two, the first bus controlling the conversion mode is connected to the first inputs of the first and second elements AND, outputs which are connected respectively to the pen bubbled inputs of said first and second elements / Hilti-NO, whose second inputs are connected respectively to the first and second installation rails, first and second elements Ilin connected respectively to the second and third inputs of the first element and vtorv Ilin and input the first and secondary. a number of structures AND of the first and second element AND-OR elements, the second inputs of the first and second elements AND are connected respectively to the direct outputs D of the triggers of the last and, the first bits, in each category, except the last, the first and second inputs of the addition element modulo two connected respectively with the direct trigger of the trigger and the second bus control conversion mode, which is connected to the input element NOT, in each category, except the first, the output of the addition element modulo two is connected to the first input of the majority element the second input cat cerned connected to the output of NOT circuit, and the third input element of the majority of each bit other than the second, coupled to the output of the majority element predschushego gazr yes, the third input element of majority vt.orogo discharge element connected to the output modulo two first discharge. FIG. 1 is a diagram of a five-bit reversible counter in FIG. 2 - tab. 1-6 codes with different recalculation modes when using a five-bit reversible counter. The counter contains O-triggers, input bus 2, elements AND-OR, elements of addition modulo two; the majority elements, the first 6, the second 7 tires control the conversion mode, the elements of the IPI-HE 8 and 9J tires 10 and 11 of the installation, the element NOT 12 and the elements And 13 and 14. The clock inputs of the O-triggers are connected to the input bus 2, and the information inputs - with the outputs of the elements AND-OR 3 1-3F5, the first input of the first structures AND of which are connected respectively to the direct outputs of the flip-flops and 1, the first input of the second structures AND elements of the I-ШШ are connected respectively to the direct outputs of the flip-flops and, the bus 6 mode control recalculation is connected with the first input elements And 13 and 14, the outputs of the connectors are connected respectively to the first inputs of the elements OR-NO 8 and 9, the second inputs of which are connected respectively to the buses 10 and 11 of the installation, the outputs of the elements SH-NOT 8 and 9 are connected respectively to the third inputs, elements OR-NOT 9 and 8 and the second the inputs and the second structure of the AND-IS elements, the second inputs of the elements 13 and 14 are connected respectively to the direct outputs of the flip-flops and, the direct outputs of the flip-flops are connected respectively to the first inputs of the ele- ments; the add-ons are 4 moduli whose second inputs are connected to the bus 7 controls In a recalculation mode, which is connected to the input of the HE element 12, the outputs of the adding elements modulo-two are connected respectively to the first inputs of the majority elements, the second inputs of which are connected to the output of the HE element 12, the third inputs of the majority elements are connected respectively to the outputs of the addition element mod- elly two and majority elements and. . : The device works as follows. Before each of the six possible modes of operation of the proposed device, by a common command, one of its O-triggers (for example, D-trigger) via the .S and K inputs of the asynchronous installation is set to one (1), and all other O-. triggers to zero (O) logical states. At the same time, the dp of providing the first four modes applies a zero logic level to bus 6 (FIG. 2, Tables 1–4), and for the last two modes, a single logic level (FIG. 2, Tables 5 and 6). Tire 7 in the first, third and fifth modes (Fig. 2, Tables 1, 3 and 5) is applied single, and in the second, fourth and sixth modes (see, Fig. 2, Tables 2, 4, 6 ) zero potentials. During the first four operation of the device (Fig. 2, Table 1-4), the presence of a zero potential on the bus 6 provides either a single or zero static condition of the short-circuit trigger on the elements ILITNE, 8 and 9, depending on previously attached to the tires 10 and 11 logical potentials (i.e., from a combination of the attached codes 01 or 10). Due to this, the outputs of the device (outputs of the elements and) ensure the formation of various forward and inverse unit codes (Tables 1–4, Fig. 2). In the last two modes (Fig. 2, Tables 5 and 6), the presence of a single potential on bus 6 provides alternate switching of the R8 trigger as the shifted (according to the O triggers) unit is reached to the extreme bits (up to the first bits and bits) As a result, at the outputs of the elements, the first or second direction of the formation of reversible unit codes is provided depending on the potential level applied to the bus 7 (Fig. 2, Tables 5 and 6). During the first two modes of operation, due to the zero potential applied to the bus 6 (and thus, excluding the elements of And 13 and 14 from the operation process of the device, as well as logical potentials applied to the tires 10 and 11, respectively

CiO and 1, at the outputs of BS -cials at the second inputs of the elements And

trigger (at the outputs of the elements OR-13 and 14.

NOT 8 and 9) are set accordingly. This allows, in turn,

logical levels 1 and O. change the original direction

This makes it possible to synchronize the clockwise pulses in addition to the block 2 in order to provide an annular shift to the reverse.

to the right, the prerecorded ones 5–5–5 in the device are performed by the functional 1 in the first L-trigger 1 1 of the code converters. Wherein

and four O in the remaining D-Trig-H elements 4 "add modulo

Herahs (Tables 1 and 2). At zero potential on bus 7, in contrast to this, the third one performs the transfer functions in its fourth mode of operation due to the direct code moves from the D-triggers, and

Applied to tires 10 and 11, respectively, with a single potential - their corresponding logical potential code. The majoritarian elements and O (with the same zero at-5 3 with zero on the bus 7 do

tire strength 6), at the outputs of the E-function of the logic element And, and

Copies 8 and 9 are set accordingly — with a unit — the functions of the logical

Stvenvenko potentials O and 1, It is an element OR,

creates conditions for ensuring the sequence 0

(in time with the post-clocking of clocking-forming processes at the outputs

pulses across the bus 2) ring shear unit codes in each

left recorded in the D-triggers to-from table. 1-6 (M 5) in FIG. 2 pokada (tab. 3 and 4). Intermittently repeated codes

In the last two modes, in the outputs of the elements of different logistic results, there are 6 unit stages on the bus (at the outputs of the O-triggered potential in the process of function-1, elements

The device includes both modulo two folding logs and endpoints

chesky elements of shsh-not b and 9. This output device (out. 1 - out. 4)

allows to carry out periodic 30t.e. at the outputs of the elements and. switching ftS-trigger on elements

8 and 9 (every five cycles, in this way, the proposed step of clocking impulses

not 2) as the ring shifts, the codset of the modes of forming a unit of the appearance of a unit in the extreme bits is the codes, which expands its functionals of the () triggers and changes in the potential possibilities.

TaVl. 1, / o.

Codes for tkty on.

Hmi on Vykhodakh Dak elekhodah Striggero

Vsh.1-Vyh.n-1 cops M2

Tab. 2

10,000

01/7

/ ohm;

about 1 about 00

I1 about 1 11 00 g 00

II101

00010

00001 11110

10,000 01111

01000 10111

00100 1 1011

00010 11101

00001 11110

Tab.Z,,

Ta5l.1, Sh-O.

Codes on

Koffiji on

codes on outputs, by-pass yojoaah 1PemkntoON1 OUT. 1 -etiX .n-1 b-triggergero

1000 o

10,000

00Q about 1

00001 00010

0001о 001 00 00100 01000

01000 10000 10000 00001 00001 00010 00010 00100 00100 01000 01000 10000 10000

TaVl. five, .

 t

Noah on. the codes on the bytes would be ebixoaax triggers heroV pemengobn, vykh.1-8kh.N-1

Tal 6, U2-0

codes on.

Nooy on

byhodah bykhadah

triggers zlementosh

10,000

01111 10111 01000 00 TOO 1 1 D 1 I 00010 1 1101 11110 00001 000 10 1 1 t 01

00100 11011 01000 10111 10000 01111 01000 10111

00100

I1 and G1 00010

11101 00001

II1 1 Q 00010 1 1 1 Q1

about about 1 about about 11011

about 1 about about Q 10111 10 000

about 1 1 i 1

10,000

1 GS about 01000

01000 00100 00100 00010 00010 00001 00001 00010

0001о

00100 00100

01о о о

1000 10,000 1 o o 0.0 01000 01000 00100 o 01 DO 00010 00010 00001 0000 00010 00010 00100 00 i 00 01800

0J 000 1 0000

1 000

Claims (1)

A REVERSE COUNTER containing an input bus, two control buses for the mode of conversion and and bits, each of which contains an AND-OR element and a J) trigger having asynchronous inputs, the clock and information inputs of which are connected respectively to the input bus and the output of the element I-IPI, the first inputs of the first and second structures AND of which are connected respectively to the direct outputs of the D-triggers of the previous and subsequent discharges in the ring of discharges, the second input of the first structure AND of the AND-OR element of the first category is connected to the second inputs of the of structures AND AND-OR elements of the remaining bits, the second inputs of the second structures AND AND-OR elements of which are connected to the second input of the second * structure AND of the AND-OR element of the first category, which means that, in order to expand the functionality by providing reversible single conversion codes, two installation buses, two AND elements, two OR-HE elements, an NOT element are entered into it, and in every digit, except the first and last, there is an addition element modulo two and ma. a fire element, an addition element modulo two is introduced into the first bit, the first bus for controlling the conversion mode is connected to the first inputs of the first and second elements AND, the outputs of which are connected respectively to the first inputs of the first and second elements OR-HE, the second inputs of which are connected respectively to the first and the second installation bus, the outputs of the first and second elements OR-HE are connected respectively to the third inputs of the second and first elements OR-HE and the second inputs of the first and second structures AND of the AND-OR element of the first so, the second inputs of the first and second AND gates connected respectively to the direct outputs of D-flip-flops of the first and last bits in each stage, except the last, the lane ⁵ ": vy and second inputs of addition modulo two elements are connected respectively to the direct output in -triggera and a second bus for controlling the recalculation mode, which is connected to the input of the element NOT, in each category, except the first, the output of the addition element modulo two is connected to the first input of the majority element, the second input of which is connected to the output of the element NOT, and the input of the majority element of each category, except for the second, is connected to the output of the majority element of the previous category, the third input of the majority element of the second category is connected to the output of the addition element modulo two of the first category. SU ..., 1145477