SU1104572A1 - Device for receiving information - Google Patents

Abstract

A DEVICE FOR RECEIVING INFORMATION, containing a receiver, the output of which is connected to the inputs of the unit selector and the selector zero, whose outputs are connected to the corresponding inputs of the OR element, the output of the unit selector is connected to the first input of the first memory block, the first delay element whose output is connected to the first input the first trigger, the first pulse counter, the output of which is connected to the first input of the element I, the second memory block, characterized in that, in order to increase the information content of the device and its reliability Oty, a descrambler, a trigger, counters, a delay element, a pulse generator, and NAND elements are introduced into it. a block of actuators and a clock pulse shaper, the output of which is connected to the first inputs of the first NAND element, the second trigger, the first pulse counter and the second input of the first memory block, whose outputs are connected respectively to the first inputs of the second memory block, whose outputs are connected respectively with the inputs of the block of actuators, the outputs of the pulse generator and the first element AND-NOT are connected respectively with the first and second inputs of the second pulse counter, the first output of which connected to the first inputs of the decoder and the third pulse counter, whose outputs are connected respectively to the second inputs of the decoder, whose outputs are connected respectively to the second inputs of the second memory block, the first and last outputs of the decoder and the second input of the first trigger, respectively; which is connected to the second inputs of the third pulse counter, the first element of NAND, the element AND, and the first inputs of the second, (L of the third and fourth elements of NAND, the second the output of the second pulse counter is connected to the second input of the second NAND element, the output of which is connected via the second delay element to the second input of the third NAND element whose output is connected to the second input of the first pulse counter and the second input of the second trigger, the output of which is connected to the first inputs of the fifth and sixth NAND elements, the outputs of which are connected respectively to the third input of the second trigger and the second input of the fourth NAND element, the output of which is connected to the third input of the second memory block, to the fourth input of which is connected to the output of the AND element, the output of the first pulse counter is connected to the second input of the sixth AND-NOT element, the output of the OR element is connected to the input of the clock pulse generator, the output of the unit selector is connected to the second input of the fifth AND-NOT element.

Description

The invention relates to the field of receiving and transmitting information and can be used to receive information transmitted in binary code at a central point in systems with a large number of receivers and transmitters operating in a common communication channel. A device for recording information is known, which contains a receiver, the output of which is connected to the input terminal of the device, the output of the receiver is connected to the inputs of the selector for the code sign of the unit and the selector for the code sign zero lj. The disadvantage of this device is low reliability of operation, due to the complexity of the design and the impossibility of recording the code signals in the presence of interference. The closest technical solution to the invention is an arrangement for receiving information, which contains a receiver, the output of which is connected to the inputs of the unit selectors and zero, the output of the selector zero is connected to the first input of the OR element, the output of the selector of the unit is connected to the second input of the OR element and the first input of the first memory block of the shift register, the delay element whose output is connected to the first input of the first trigger, the first pulse counter, the output of which is connected to the first input of the And element, the second memory block, the block with 2. The disadvantage of the known device is its limited functionality, since when used in systems with n-series transmitters, each of which transmits W-information in one cycle of operation, the device located at the central point does not allow to make a selective recording in the memory of information received from each transceiver (local telemechanics center), and also to monitor it during operation. The purpose of the invention is to increase the information content of the device and the reliability of its work. The goal is achieved by the fact that the device for receiving information containing the receiver. 22 whose output is connected to the inputs of the unit selector and the zero selector, the outputs of which are connected to the corresponding inputs of the OR element, the output of the unit sapector is connected to the first input of the first memory block, the first delay element whose output is connected to the first input of the first trigger, the first pulse counter , the output of which is connected to the first input of the element And, the second block of memory, entered a decoder, a trigger, counters, a delay element, a pulse generator, elements of NAND, a block of actuators and a driver clock and pulses whose output is connected to the first inputs of the first NAND element, the second trigger, the first pulse counter and the second input of the first memory block, the outputs of which are connected respectively to the first inputs of the second memory block, the outputs of which are connected respectively to the inputs of the actuator block, the outputs of the pulses and the first element AND-NOT are connected respectively to the first and second inputs of the second pulse counter, the first output of which is connected to the first inputs of the decoder and the third counter imp pulses, the outputs of which are connected respectively to the second inputs of the decoder, the outputs of which are connected respectively to the second inputs of the second memory unit, the first and last outputs of the decoder are connected respectively to the input of the first delay element and the second input of the first trigger, whose output is connected to the second inputs of the third counter pulses, the first element AND-NOT, the element AND and the first input of the second, third and fourth elements AND-NOT, the second output of the second pulse counter is connected to the second input of the second element That NAND, whose output is connected via the second delay element to the second input of the third NAND element, the output of which is connected to the second input of the first pulse counter and the second input of the second trigger, the output of which is connected to the first inputs of the fifth and sixth AND NAND The outputs of which are connected respectively to the third input of the second trigger and the second input of the fourth NAND element, the output, which is connected to the third input of the second memory block, to the fourth input of which the output of the And element is connected, the output of the first impu counter sov connected to the second input of the sixth AND-NO element, an output of OR is connected to an input of a clock selector unit output is connected to the second input of the fifth AND-member,

The drawing shows the functional diagram of the device.

The device contains a receiver 1, selector unit 2, selector 3 zero element OR 4, first memory block 5 second memory block 6, first 7 and second 8 triggers, first 9, second 10 and third 11 pulse counters, first 12 and second 13 delay elements, element 14, pulse generator 15, decoder 16, first 17 second 18, third 19, quarter-20, fifth 21 and sixth 22 AND-NOT elements, block 23 of actuators and driver 24 clock pulses.

The device operates cyclically. Each cycle is divided into P-subcycles according to the number of transceivers, local telemechanics points connected to a common communication channel. During each subcycle, gp-bi information is received.

The number (p) of the outputs of the decoder 16 is equal to the number of local telemechanics points connected to the common communication channel. The number of outputs of the third counter 11 pulses is greater than (or equal to) the number of bits needed to represent the number of local telemechanics points in binary calculus. The number (w) of the outputs of block 5 and the appearance at the output of the first counter 9 of pulses of the level of a logical unit depend on the number of bits of information received from each local telemechanic station.

The device works as follows.

When the supply voltage is applied, the first delay element 12 is triggered, the second delay element 13 is set to the initial, single state, and the first trigger 7 is set to the initial, zero, state, thereby prohibiting the operation of And 14, the first 17, the second 18, third 19

and the fourth 20 elements of the IS-NOT and the third pulse counter 11. Pulses. The first delay element 12 is designed to detune from the time required to prepare

the first local telemechanic station to transmit frj-bit information to the central point. The second delay element is designed to offset from the time during which the address of the local telemechanic station is transmitted. At the output of the third element, NAND 19, the level of the logical unit appears,

which arrives at the third input of the second trigger 8 and prepares it for actuation, as well as at the input of the first counter 9 pulses, sets it to the initial, zero,

state and allows it to work. The level of the logical unit from the output of the second trigger 8 arrives at the second input of the fifth element NAND 21 and prepares it for passing information from the output of the selector 2 units to the first input of the second trigger 8. The level of the logical unit from the output of the second trigger 8 is also fed to the first input of the sixth

element AND-NOT 22, to the second input of which, from the output of the first counter of 9 pulses, a signal arrives with a logic level of zero, which prohibits the operation of the element AND-NOT 22 and

sets the output level of the logical unit. The signal from the output of the first pulse counter also prohibits the operation of the element 14.

At the output of the first element AND-NOT 17, the level of the logical unit is set to prohibit the operation of the second counter 10 pulses. Moreover, at both outputs of this counter levels of logical units are set. The level of the logical unit from the output of the second counter 10 pulses is fed to the first input of the third counter 11 pulses and to the input of the decoder 16, allowing the latter to work. The level of the logical unit from the output of the second counter 10 pulses is fed to the input of the second element AND-NOT 18, preparing it

to work.

This completes the preparation for the first cycle of the device for receiving information. 5 At the expiration of a predetermined time lag, the output of the first delay element 12 appears at a logic zero level, which sets the first trigger 7 to the single state. The level of the logical unit from the output of this trigger arrives at the corresponding inputs of the element AND 14, the first 17, the second 18 the third 19 and the fourth 20 AND-NOT elements and allows their operation. In this case, the third counter 11 of the pulse is set to the initial, zero state, which corresponds to the address of the first local telemechanic station. The signals from the output of this counter are fed to the corresponding inputs of the decoder 16, the first output of which has a signal with a logic zero level, which prohibits the operation of the first delay element 12 and prepares the corresponding cell of the memory block 6 for recording information from the first local telemechanic station. At the outputs of the second 18 and third 19 NAND elements logic level zero levels appear, the first of which triggers the second delay element 13, and the second enters the input of the second trigger 8, setting this trigger to its original, single state and prohibiting its operation , and to the second input of the first counter 9 pulses, also prohibiting its operation. The level of the logical unit arrives at the second input of the pto element I-HE 21, preparing it for production of pulses from the output of the selector 2 units to the first input of the second trigger 8. The high signals of the selectors 2 and 3 have the values of logical zero, and the signal from the output of the former 24 clock pulses, intended to form short pulses, has a value of logical one. The transmitted signals (the address of the local telemechanic center and information from it) are received by the receiver 1 connected to the communication channel (not fixed), and are fed to the inputs of the selectors. When a unit code appears in any bit of a bit, the potential at the output of the selector 2 units when 726 acquires the value of a logical unit, and the value of logical zero remains at the output of the selector 3 zero. When a code zero appears in any bit at the output of the selector 2 of the unit, a logical zero signal appears, and at the output of the selector 3 the potential of the logical unit zero. Since the outputs of both selectors are connected to the inputs of a logical element OR 4, the potentials of a logical unit appear at its output when any elementary parcel containing a code feature enters the device. These pulses are fed to the input of the clock maker 24 clock pulses, which form short pulses of logic level zero from the incoming pulses. Via. newly formed pulses are: recording information in block 5 in accordance with the code values received at the input of block 5, random advancement of previously recorded information, with each shift clock pulse corresponding to a shift of the number recorded in the block by one bit dJ switching the first counter 9 pulses when receiving information from the local telemechanic point j clocking the second trigger 8, as well as setting the second counter 10 pulses to the initial single state. Upon expiration of the time during which the address of the local telemechanical center is transmitted, the output of the second delay element 13 appears at a logic zero level, which arrives at the second input of the third IS 19 element and sets the logic one level at its output. The level of the logical unit from the output of the third element IS 19 is supplied to the corresponding inputs of the second trigger 8, preparing it for operation, and the first counter 9 pulses, setting it to the initial, zero, state and enabling the counting of clock pulses to the first input of this counter from the generator 24 output. If there is at least one unit in the code received from the local telemechanic station, which signals, for example, that the monitored parameter is out of acceptable limits, the output potential is The lecturer 2 units acquires the value of a logical unit and arrives at the first input of the fifth element AND-NOT 21. At the output of the fifth element AND-NE 21, a level of logical zero is set, which goes to the first input (D-input) of the second trigger 8. With the arrival a clock pulse to the input (C-input) of the trigger 8, its state changes, i.e. at the output, a logic zero level appears, which enters the second input of the fifth IS-NOT element 21 and prohibits its operation.

 In the absence of units in the code, the potential at the output of the selector 2 does not change the unit of its state, i.e. it remains at the logic zero level. Therefore, the initial, single state of the second trigger 8 also does not change.

When the first counter 9 pulses the number m at its output, the level of the logical unit appears, which is fed to the second input of the sixth AND-HE element 22 and to the input of the AND 14 element, allowing the operation of these elements. At the same time, the level of the logical unit that arrives at the input of memory block 6 and allows information to be written to this block from the outputs of block 5 and the output of the fourth element AND –NE 20 into the memory cell that is open appears at the input of the element 14. the level of logical zero from the output of the decoder 16.

Moreover, if the initial, single state of the second flip-flop 8 is not changed, which corresponds to the absence of ones in the received code, then the output of the sixth element IS-HAN 22 is set to a logic zero level. This level is fed to the input of the fourth element AND-NOT 2U and the mouth; it pours the level of a logical unit at its output.

If the initial, single, state of the second trigger 8 changes, i.e. a logical zero level appears at its output, which corresponds to the presence of at least one unit in the received code, then the level of the logical unit is saved at the output of the sixth element AND-NOT 22, and the level at the output of the fourth element IS-NOT 20 logical zero.

Thus, in the first case, the level of the logical unit is recorded in the corresponding cell of the memory block 6, which corresponds to the state of the monitored parameter within the specified limits. In the second case, the logical zero level is recorded in the same cell, which corresponds to the output of the monitored parameter from the specified limits, i.e. The proposed device makes control of information coming from each local telemechanic center, which increases the reliability of receiving information.

Preparation of the device for receiving information for the next work cycle occurs as follows.

Upon completion of the transfer of information

0 there is a dead time pause from the first (or previous) local telemechanics point in the communication channel (not shown), so there are no signals at the output of receiver 1. Consequently, at the outputs of selectors 2 and 3 and the element OR 4, the level of logic zero is maintained, and at the output of the generator of 24 clock pulses, the level of a logical unit. As a result, at the output of the first AND-N-17 element a logical zero level appears, which sets the second counter of 10 pulses to the initial, single, state and enables its operation. When typing second

5 by a counter 10 Pulses of a predetermined time lag, equal to the time required for preparing the transmitter of the central telemechanic center (not shown) to transmit the address

0 of the next in order address of the local telemechanic center, at its first output a logical zero level is set, which prohibits the operation of the third counter of 11 pulses and the decoder 16.

In this case, in the case of receiving information in the previous sub-cycle from the first local telemechanic station, the level of the logical unit is again set at the first output of the decoder 16, and the first delay element 12 is launched.

five

The pulse from the generator output is 15 pulses, following the one that sets the logical zero level at the first output of the counter 10. sets the level of logical nl and at the second output of this counter the level of logical zero from the second output of the second counter 10 impulse sets the second element IS-NOT 1 to one state. The level of the logical unit from the output of the second element I-IC 18 prohibits the operation of the second delay element 13. This completes the preparation of the device for receiving information for the new work sub-cycle. When receiving the address of the next (1st) local telemechanic center and then the information from it, the first and subsequent pulses from the output of the driver 24 clock pulses set the second counter 10 pulses to the initial, single state. The level of the logical unit from the first output of this counter enters the first input (C-in of the third counter 11 pulses, changing its previous state to one, which corresponds to the address of the 1st local telemechanic center, and forbidding the input of the decoder 16, allowing its operation. As a result, a logic zero level appears at the output of the decoder 16, which prepares the corresponding cell of the memory block 6 for information recording received by the local telemechanic ci -rcf. The level of the logical unit from the second output is second the pulse counter 10 is fed to the second input of the second element AND-HE 1B and sets at its output a logic zero level that triggers the second delay element 13. After a time during which the address of the local telemechanic center is received, the output of the second delay element 13 is is the level of logical zero, which is fed to the second input of the third element IS-NOT 19 and sets the level of the logical unit at its output. The level of the logical unit from the output of the third element IS 19 is supplied to the corresponding inputs of the second trigger 8, preparing it for operation, and the first counter 9 pulses, setting it to its original, zero state and enabling counting the clock pulses to the first input of this counter from the output of the driver 24 clock pulses. The recording of the received information from the i-th local telemechanic center into the corresponding cell of memory block 6, its monitoring, as well as preparation for a new sub-cycle of the device operation is carried out similarly to that described. After receiving and recording information from the last nth local telemechanic site, a signal from the last (Nth) output of the decoder 16 first trigger 7 is set to the initial, zero state. The operation of the device for receiving information in this subcycle terminates. . After the time required to prepare the first local telemechanic station for a new information transfer-cycle, the logic zero level appears at the output of the first delay element 12, which sets the first trigger 7 to one state. The operation of the device for receiving information in the new cycle is repeated. Execution unit 23 is intended for processing information recorded in memory unit 6. By means of block 23, for example, an indication of the state of the monitored parameter is carried out for each local telemechanics station. Thus, in the present invention, due to the introduction of additional elements and new connections, selective recording is made of information received from each local telemechanics point into the memory, as well as its control is performed, which increases the information content of the device and the reliability of its operation.

Claims (1)

A device for receiving information containing a receiver whose output is connected to the inputs of the unit selector and zero selector, the outputs of which are connected to the corresponding inputs of the OR element, the output of the unit selector is connected to the first input of the first memory block, the first delay element, the output of which is connected to the first input of the first trigger, the first pulse counter, the output of which is connected to the first input of the And element, the second memory unit, characterized in that, in order to increase the information content of the device and the reliability of its operation, not The decoder, trigger, counters, delay element, pulse generator, AND elements are introduced. a block of actuating elements and a driver of clock pulses, the output of which is connected to the first inputs of the first element AND, the second trigger, the first pulse counter and the second input of the first memory block, the outputs of which are connected respectively to the first inputs of the second memory block, the outputs of which are connected respectively to the inputs block of actuators, the outputs of the pulse generator and the first element are NOT connected respectively to the first and second inputs of the second pulse counter, the first output of which is connected n with the first inputs of the decoder and the third pulse counter, the outputs of which are connected respectively to the second inputs of the decoder, the outputs of which are connected respectively with the second inputs of the second memory block, the first and last outputs of the decoder are connected respectively to the input of the first delay element and the second input of the first trigger, whose output is connected to the second inputs of the third pulse counter, the first AND-NOT element, the AND element and the first inputs of the second, third and fourth AND-NOT elements, the second output of the second the pulse detector is connected to the second input of the second AND-NOT element, the output of which through the second delay element is connected to the second input of the third 'AND-NOT element, the output of which is connected to the second input of the first pulse counter and the second input of the second trigger, the output of which is connected to the first inputs of the fifth and sixth AND-NOT elements, the outputs of which are connected respectively to the third input of the second trigger and the second input of the fourth AND-NOT element, the output of which is connected to the third input of the second memory unit, to the fourth input of which connected to the output of AND gate, the first pulse counter output is connected to the second input of the sixth AND-NO element, an output of OR is connected to an input of the clock pulse, the output unit selector is connected to the second input of the fifth AND-NO element. SUL · "» 1104572