SU1012260A1 - Computer error diagnostic device - Google Patents

Abstract

DEVICE FOR THE DIAGNOSTICS OF ERRORS OF A COMPUTER f Containing Nodes. I / O channels, timer,. Shaper signal generalized. errors, blocking Triggers group, block of Registrant States, reset block and sshb trigger, the Timer output is connected to the first input of the trigger, the first output of the reset block is connected to the first inputs of the generator of the generalized signal, the blocking trigger of the group and the input of the state register, and the second output is the output of the interrupt 1: 1) of the device, the input of the reset unit is connected to the input of the state registration unit, the output of the signal conditioners of a significant error is connected to the second inputs of the trigger triggers The groups which outputs are the device synchronization interlocking outputs are required so that, in order to maintain the reliability of the computer due to automatic recovery of the processor, in case of a processor hang, an OR element is given, a delay element, a group of elements AND and a group of elements OR, - the first and second inputs of the OR element are connected respectively to the trigger output from the output and the device error input / g and the output is connected to the second input of the generalized error signal generator, the first output b A reset through the delay element is connected to the timer input and the second error trigger input, the output of which is connected to the first chops of the AND elements of the group, the second inputs of which are connected to the device channel selection bus, and the outputs are connected to the first inputs of the elements, OR groups, the second inputs which are connected to the dumping bus. device channels, and the outputs are connected by d inputs of nodes for resetting channels of input and output.

Description

The invention relates to the field of computing and can be used in computers, including processors and input-output channels. A diagnostic device is known comprising a monitoring and diagnostic unit and an interval timer unit, which is connected to the central control unit and to the memory control unit. The device automatically handles the errors fixed by the processor control circuits, i.e. hardware repetition of the seo situation is performed and the extended registration of the state of the processor I is performed for the subsequent software repetition at the level of the operating system. In this row, the device allows determining the d: 1 beeps that are not fixed by the processor control circuits that cause the processor to hang for indefinite time 1 A disadvantage of the known device is the impossibility of automatically handling errors of this type (hang errors). The closest in technical essence to the present invention is a diagnostic device, a data processing system comprising a monitoring and diagnostics unit, an interval timer unit, a hang error trigger, a memory management bus, an update request bus, a reset bus, a processor hardware error bus, processing processor start bus, channel selection bus, system reset bus, the first input of the monitoring and diagnostics unit is connected to the processor hardware error bus, the first output of the monitoring and diagnostics unit and connected to the start-up bus of the processing microprogram, the first input of the interval timer block is connected to the reset bus, the first output of the interval timer block is connected to the memory control bus, the second output of the interval timer block is connected to the update request bus, the third output of the interval timer block is connected to the setup the trigger input of the hang error 2. This device automatically handles the errors detected by the processor control circuits and determines the hang errors. Hangup may be due to hardware malfunction. the processor (the less likely the cause) and malfunctioning I / O hardware is more likely to cause. I / O means channels and I / O devices. If the hangup error is caused by the failure of the I / O equipment, in order to eliminate the cause of the hangup, manual intervention by maintenance personnel is required, in which the computational continuity is interrupted. Moreover, the time spent on the restoration of system performance can be significant, since it depends on the qualifications of the staff. If the hangup error is caused by a failure in the processor hardware, then the system also does not automatically recover. The disadvantage of the device is the inability to automatically handle hang errors and. restore the operability of the data processing system without the fate of service personnel The purpose of the invention is to increase the reliability of a computer due to automatic recovery in the event of a processor hang. The goal is achieved in that a device containing I / O channel reset nodes, a timer, a generic error signal generator, a block of trigger triggers, a state registration block, a reset block, and an error trigger, the timer output connected to the first error trigger input the output of the reset unit is connected to the first inputs of the generalized error signal conditioner, the group lock triggers and the state registration unit input, and the second output is the output of the device interrupt the input of the reset unit is connected . the output of the state registration unit, the output of the signal generator of the generalized error is connected to the second inputs of the group lock triggers, the outputs of which are the device synchronization lock outputs, the OR element, the delay element, the N element group, the OR element group, and the first and second OR element inputs are connected respectively, with the output of the error trigger. and the error input of the device, and the output is connected to the second input of the sig- er shaper; Generalized error, the first output of the reset unit through the delay element is connected to the timer input and the second error trigger input, the output of which is connected to the first inputs of the group, the second inputs of which are connected to the device channel selection bus, and the outputs are connected to the first inputs of the elements of the OR group, The monitor inputs of which are connected to the device channel reset bus, and the outputs connect. Neva of the reset nodes enter the output. . i.Ha image of the device; 2, the temporal diagrams. The device contains an element OR 1 timer 2 / shaper 3 generalized error signals -, delay element 4 / trigger 5 error, group of elements AND 6, rpyntiy of elements OR 1, NODES 8 reset of input-output channels group of blocking triggers 9 blocks of 10 registration, state 11 ebrsa, error input 12, synchronization blocking output 13, interrupt output 14, bus 15 (channel selection i, i iin 16 channel reset i water-out), selective reset bus 17, processor reset output 18, output 19 sat Ca channel. FIG. 2 are designated: failure of input / output channels causing processor 20 to freeze, phase. performing the registration of the state of the processor 21, the execution phase of the Mick of the computer error processing program 22, the execution phase of the recovery program 23.,. The device works as follows. In normal operation of the processor (the drawing is not shown) ,. i.e. in the case of the absence of unplanned firmware, requests for updating timer 2 intermittently also match the value of the counted time, stored with in timer 2, does not exceed a non-. control value. In case of a deviation from the mormal operation, the update cannot be started, which leads to k exceeding by the timer 2 the maximum permissible time value. This sets the 1 Trigger value to Trigger 5. This situation is defined as a hang process. The hang is a consequence of the hardware faults of the channel or I / O means and is manifested as an I / O command looping on the MMRp programs or on the npepbts processing firmware of the I / O Institute, while waiting for the response of the channels. If a hang occurs, after a error is detected, the signal from the output of trigger 5 through the element OR 1 is fed to the driver of the driver 3. This will lock the synchronization lock S in the process (output 13). At the same time, the extended state registration begins in block 10, which consists in storing the values of the registers and control triggers into a fixed area of the operational memory (memory not shown). The input is trizgge; ra 5 sv head also with the inputs of the elements of the b and b group which provide a separate reset of the input-output channels. The other inputs of the And 6 elements are connected to the channel selection channel 15. When executing commands in the input, one of the kangshovs is selected by the process by a single channel selection signal in the corresponding bus 15, as a result of which the selective reset signal is fed to the corresponding element OR 7 and further to the input of the corresponding node 8, where it sets KaHaj to the ready state. Yes)) The channel state is initial for its subsequent launch, according to the appropriate I / O instruction. After the registration phase is completed, the processor reset phase is executed, at the beginning of which all main registers and processor triggers are reset to the HT1e state, and all T | 1 O1 | Lbock trigger points, including trigger 5, are reset to zero. Simultaneously with resetting the processor, the synchronization lock of the processor is released. In order to eliminate the possibility of reinstalling trigger 5, the overflow counter, which is part of timer 2, is reset in parallel. The end of the bus signal is associated with the start of the processor reset phase. Thus, to ensure stable operation at the edges of the signals on bus 15, i.e. in order to exclude the possible start of the channel with the corresponding-signal-. On the bus 15 at the moment of termination of the signal at the output of the trigger 5, the necessary element Ze1de | 4 This element provides a delay of 8 as element 4. You can use the well-known D-Trig- scheme. Hera. After the end of the processor reset phase, block 11 generates a signal to the startup bar of the processed firmware, as a result of which the microprogramme of the hang error is started. This firmware generates a code for control over {) and implements the transfer of control to the recovery system of the operating system. In {a case of the named program, all information is needed, obtained as a result of registration, allowing repeated

Start the I / O operation that caused the hang.

When forming a signal, a selective reset will always maintain a temporal relationship (see fig, 2)

where t. - the maximum value of the execution time of the operations in the processor is allowed, not the value of the formation

sign of hangup; t - cykiMapHoe processing time

errors, Kotoiioe is drained from the time of the registration phase, the processor reset phase and the microprogram operation phase of the Machine Error.

The proposed device makes it possible to increase the reliability of a computer for automatically restoring the System to its operability —With depending on the processor, due to the failure of the equipment of the HJiH means of the processor. Understand the reliability of a computer is achieved by a slight increase in hardware gaps.

Phie.

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Claims (1)

DEVICE FOR DIAGNOSTIC OF COMPUTER ERRORS, containing nodes of reset of input-output channels, timer, signal conditioner generalized. errors, a group of Blocking Triggers, a State registration block, a reset block, and an error trigger, with the timer output connected to the first input of the error trigger, the first output of the reset block connected to the first inputs of the generalized error signal generator, blocking triggers of the group th input of the state registration block, and the second the output is the interrupt output of the device, the input of the reset unit is connected to the input of the state registration unit, the output of the generalized signal generator is connected to the second inputs of group blocking triggers , KOTOpbIX OUTPUTS are the outputs for locking the device’s synchronization, furthermore, in order to increase the reliability of the computer by automatically restoring operability in the event of a processor freeze, an OR element is introduced into it, an element of 'delay, a group of AND elements and a group of OR elements, moreover, per. 'the second and second inputs of the OR element are connected respectively to the error trigger output and the device error input /, and the output is connected to the second input of the generalized error signal generator, the first output of the reset unit through the delay element is connected to the timer input and the second input of the error trigger, * output which is connected to the first inputs of the elements AND groups, the second inputs of which are connected to the device channel selection bus, and the outputs are connected to the first inputs of the JUIH elements of the group, the second inputs of which are connected to the device reset bus properties, and the outputs are connected about the inputs of the reset nodes of the input-output channels. 8 ω St