SG84090G - Ttl to cmos input buffer - Google Patents

Ttl to cmos input buffer

Info

Publication number
SG84090G
SG84090G SG840/90A SG84090A SG84090G SG 84090 G SG84090 G SG 84090G SG 840/90 A SG840/90 A SG 840/90A SG 84090 A SG84090 A SG 84090A SG 84090 G SG84090 G SG 84090G
Authority
SG
Singapore
Prior art keywords
ttl
input buffer
cmos input
cmos
buffer
Prior art date
Application number
SG840/90A
Other languages
English (en)
Original Assignee
American Telephone & Telegraph
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by American Telephone & Telegraph filed Critical American Telephone & Telegraph
Publication of SG84090G publication Critical patent/SG84090G/en

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175Coupling arrangements; Interface arrangements
    • H03K19/0185Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507Interface arrangements
    • H03K19/018521Interface arrangements of complementary type, e.g. CMOS
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008Arrangements for reducing power consumption
    • H03K19/0013Arrangements for reducing power consumption in field effect transistor circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Power Engineering (AREA)
  • Logic Circuits (AREA)
SG840/90A 1985-05-28 1990-10-18 Ttl to cmos input buffer SG84090G (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US06/738,593 US4672243A (en) 1985-05-28 1985-05-28 Zero standby current TTL to CMOS input buffer
PCT/US1986/000992 WO1986007220A1 (en) 1985-05-28 1986-05-05 Ttl to cmos input buffer

Publications (1)

Publication Number Publication Date
SG84090G true SG84090G (en) 1990-12-21

Family

ID=24968652

Family Applications (1)

Application Number Title Priority Date Filing Date
SG840/90A SG84090G (en) 1985-05-28 1990-10-18 Ttl to cmos input buffer

Country Status (10)

Country Link
US (1) US4672243A (zh)
EP (1) EP0223786B1 (zh)
JP (1) JPS62502931A (zh)
KR (1) KR940003809B1 (zh)
CN (1) CN1005674B (zh)
CA (1) CA1252521A (zh)
DE (1) DE3673342D1 (zh)
IE (1) IE57339B1 (zh)
SG (1) SG84090G (zh)
WO (1) WO1986007220A1 (zh)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS635553A (ja) * 1986-06-25 1988-01-11 Fujitsu Ltd バツフア回路
JPS6355797A (ja) * 1986-08-27 1988-03-10 Fujitsu Ltd メモリ
US4841175A (en) * 1987-01-23 1989-06-20 Siemens Aktiengesellschaft ECL-compatible input/output circuits in CMOS technology
US4763021A (en) * 1987-07-06 1988-08-09 Unisys Corporation CMOS input buffer receiver circuit with ultra stable switchpoint
JPH0197014A (ja) * 1987-10-09 1989-04-14 Toshiba Corp 半導体集積回路
JP2585348B2 (ja) * 1988-02-22 1997-02-26 株式会社東芝 不揮発性半導体記憶装置
US4980583A (en) * 1989-01-03 1990-12-25 National Semiconductor Corporation CMOS level shift circuit with active pull-up and pull-down
US5084637A (en) * 1989-05-30 1992-01-28 International Business Machines Corp. Bidirectional level shifting interface circuit
US4999529A (en) * 1989-06-30 1991-03-12 At&T Bell Laboratories Programmable logic level input buffer
US5151622A (en) * 1990-11-06 1992-09-29 Vitelic Corporation CMOS logic circuit with output coupled to multiple feedback paths and associated method
JP3079675B2 (ja) * 1991-08-22 2000-08-21 ソニー株式会社 レベル変換回路
US5304867A (en) * 1991-12-12 1994-04-19 At&T Bell Laboratories CMOS input buffer with high speed and low power
EP0557668A1 (en) * 1992-02-26 1993-09-01 International Business Machines Corporation Low power TTL/CMOS receiver circuit
US5406139A (en) * 1993-03-19 1995-04-11 Advanced Micro Devices, Inc. Input buffer utilizing a cascode to provide a zero power TTL to CMOS input with high speed switching
US6002618A (en) * 1994-08-15 1999-12-14 Creative Integrated Systems NMOS input receiver circuit
JP2743878B2 (ja) * 1995-08-30 1998-04-22 日本電気株式会社 入力バッファ回路
US5703500A (en) 1996-05-15 1997-12-30 Micron Technology, Inc. Threshold voltage scalable buffer with reference level
US5847576A (en) * 1996-11-07 1998-12-08 Lucent Technologies Inc. Low power, variable logic threshold voltage, logic gates
US5955893A (en) * 1996-12-16 1999-09-21 Macronix International Co., Ltd. Power saving buffer circuit buffer bias voltages
JP3185730B2 (ja) * 1997-11-14 2001-07-11 日本電気株式会社 相補型mos半導体装置
KR100482737B1 (ko) * 1997-12-11 2005-08-24 주식회사 하이닉스반도체 에스램의라이트드라이버회로
US6087854A (en) * 1998-09-02 2000-07-11 Lattice Semiconductor Corporation High speed line driver with direct and complementary outputs
US6323701B1 (en) * 1998-12-28 2001-11-27 Cypress Semiconductor Corporation Scheme for reducing leakage current in an input buffer
JP2002064150A (ja) * 2000-06-05 2002-02-28 Mitsubishi Electric Corp 半導体装置
JP2002353805A (ja) * 2001-05-30 2002-12-06 Fujitsu Ltd 半導体回路
US6559704B1 (en) * 2001-06-19 2003-05-06 Lsi Logic Corporation Inverting level shifter with start-up circuit
US8082207B2 (en) * 2004-06-17 2011-12-20 Certegy Check Services, Inc. Scored negative file system and method
US7109755B2 (en) * 2004-10-27 2006-09-19 Intel Corporation Power delivery noise cancellation mechanism
US7768296B2 (en) * 2006-02-23 2010-08-03 Freescale Semiconductor, Inc. Electronic device and method

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US955006A (en) * 1909-01-27 1910-04-12 Joseph Everett Sparks Abdominal retractor.
US3675144A (en) * 1969-09-04 1972-07-04 Rca Corp Transmission gate and biasing circuits
US4258272A (en) * 1979-03-19 1981-03-24 National Semiconductor Corporation TTL to CMOS input buffer circuit
US4438352A (en) * 1980-06-02 1984-03-20 Xerox Corporation TTL Compatible CMOS input buffer
US4437025A (en) * 1981-07-29 1984-03-13 Intel Corporation MOS Buffer for receiving TTL level signals
US4406957A (en) * 1981-10-22 1983-09-27 Rca Corporation Input buffer circuit
US4463273A (en) * 1981-10-26 1984-07-31 Rca Corporation Electronic circuits and structures employing enhancement and depletion type IGFETs
US4421994A (en) * 1981-11-02 1983-12-20 Ibm Corporation High speed line driver with ground output capability
US4408136A (en) * 1981-12-07 1983-10-04 Mostek Corporation MOS Bootstrapped buffer for voltage level conversion with fast output rise time
US4471242A (en) * 1981-12-21 1984-09-11 Motorola, Inc. TTL to CMOS Input buffer
US4475050A (en) * 1981-12-21 1984-10-02 Motorola, Inc. TTL To CMOS input buffer
US4490633A (en) * 1981-12-28 1984-12-25 Motorola, Inc. TTL to CMOS input buffer
US4498021A (en) * 1982-07-13 1985-02-05 Matsushita Electric Industrial Co., Ltd. Booster for transmitting digital signal
JPS5990292A (ja) * 1982-11-12 1984-05-24 Toshiba Corp 電圧変換回路
US4501978A (en) * 1982-11-24 1985-02-26 Rca Corporation Level shift interface circuit
US4584491A (en) * 1984-01-12 1986-04-22 Motorola, Inc. TTL to CMOS input buffer circuit for minimizing power consumption

Also Published As

Publication number Publication date
IE861394L (en) 1986-11-28
DE3673342D1 (de) 1990-09-13
KR880700548A (ko) 1988-03-15
IE57339B1 (en) 1992-07-29
KR940003809B1 (ko) 1994-05-03
CA1252521A (en) 1989-04-11
WO1986007220A1 (en) 1986-12-04
EP0223786B1 (en) 1990-08-08
CN1005674B (zh) 1989-11-01
US4672243A (en) 1987-06-09
EP0223786A1 (en) 1987-06-03
JPH059965B2 (zh) 1993-02-08
JPS62502931A (ja) 1987-11-19
CN86103513A (zh) 1987-02-18

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