SG184747A1 - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

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Publication number
SG184747A1
SG184747A1 SG2012067898A SG2012067898A SG184747A1 SG 184747 A1 SG184747 A1 SG 184747A1 SG 2012067898 A SG2012067898 A SG 2012067898A SG 2012067898 A SG2012067898 A SG 2012067898A SG 184747 A1 SG184747 A1 SG 184747A1
Authority
SG
Singapore
Prior art keywords
impurity region
insulating layer
region
substrate
layer
Prior art date
Application number
SG2012067898A
Other languages
English (en)
Inventor
Isobe Atsuo
Godo Hiromichi
Shinohara Satoshi
Original Assignee
Semiconductor Energy Lab
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Energy Lab filed Critical Semiconductor Energy Lab
Publication of SG184747A1 publication Critical patent/SG184747A1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/411—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by materials, geometry or structure of the substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02675—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H10D30/0323—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon comprising monocrystalline silicon

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Thin Film Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)
  • Solid State Image Pick-Up Elements (AREA)
SG2012067898A 2009-03-12 2010-03-08 Semiconductor device and manufacturing method thereof SG184747A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2009059157 2009-03-12

Publications (1)

Publication Number Publication Date
SG184747A1 true SG184747A1 (en) 2012-10-30

Family

ID=42729981

Family Applications (1)

Application Number Title Priority Date Filing Date
SG2012067898A SG184747A1 (en) 2009-03-12 2010-03-08 Semiconductor device and manufacturing method thereof

Country Status (4)

Country Link
US (1) US8530333B2 (enExample)
JP (1) JP2010239123A (enExample)
CN (1) CN101840864B (enExample)
SG (1) SG184747A1 (enExample)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011029610A (ja) * 2009-06-26 2011-02-10 Semiconductor Energy Lab Co Ltd 半導体装置及びその作製方法
JP5658916B2 (ja) * 2009-06-26 2015-01-28 株式会社半導体エネルギー研究所 半導体装置
US8766361B2 (en) * 2010-12-16 2014-07-01 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and electronic device
US8643007B2 (en) * 2011-02-23 2014-02-04 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
WO2013057771A1 (ja) * 2011-10-21 2013-04-25 株式会社島津製作所 薄膜トランジスタの製造方法
JPWO2013057771A1 (ja) * 2011-10-21 2015-04-02 株式会社島津製作所 薄膜トランジスタの製造方法

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6534409B1 (en) * 1996-12-04 2003-03-18 Micron Technology, Inc. Silicon oxide co-deposition/etching process
US6534380B1 (en) * 1997-07-18 2003-03-18 Denso Corporation Semiconductor substrate and method of manufacturing the same
JPH11163363A (ja) 1997-11-22 1999-06-18 Semiconductor Energy Lab Co Ltd 半導体装置およびその作製方法
JP4126912B2 (ja) * 2001-06-22 2008-07-30 セイコーエプソン株式会社 電気光学装置及びその製造方法並びに電子機器
JP2003158270A (ja) * 2001-08-27 2003-05-30 Seiko Epson Corp 電気光学装置および電気光学装置の製造方法、並びに投射型表示装置、電子機器
JP3909583B2 (ja) * 2001-08-27 2007-04-25 セイコーエプソン株式会社 電気光学装置の製造方法
US7119365B2 (en) * 2002-03-26 2006-10-10 Sharp Kabushiki Kaisha Semiconductor device and manufacturing method thereof, SOI substrate and display device using the same, and manufacturing method of the SOI substrate
JP4794810B2 (ja) * 2003-03-20 2011-10-19 シャープ株式会社 半導体装置の製造方法
JP2005223102A (ja) * 2004-02-04 2005-08-18 Nec Corp 不揮発性記憶装置及びその製造方法
JP3998677B2 (ja) * 2004-10-19 2007-10-31 株式会社東芝 半導体ウェハの製造方法
US7456080B2 (en) * 2005-12-19 2008-11-25 Corning Incorporated Semiconductor on glass insulator made using improved ion implantation process
US7608521B2 (en) * 2006-05-31 2009-10-27 Corning Incorporated Producing SOI structure using high-purity ion shower
JP5216204B2 (ja) * 2006-10-31 2013-06-19 株式会社半導体エネルギー研究所 液晶表示装置及びその作製方法
JP2008225338A (ja) 2007-03-15 2008-09-25 Seiko Epson Corp 電気光学装置およびその製造方法、電子機器
US20080248629A1 (en) * 2007-04-06 2008-10-09 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor substrate
US7767542B2 (en) * 2007-04-20 2010-08-03 Semiconductor Energy Laboratory Co., Ltd Manufacturing method of SOI substrate
EP1993127B1 (en) * 2007-05-18 2013-04-24 Semiconductor Energy Laboratory Co., Ltd. Manufacturing method of SOI substrate
US7795111B2 (en) * 2007-06-27 2010-09-14 Semiconductor Energy Laboratory Co., Ltd. Manufacturing method of SOI substrate and manufacturing method of semiconductor device
EP2009687B1 (en) * 2007-06-29 2016-08-17 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing an SOI substrate and method of manufacturing a semiconductor device
JP2009043748A (ja) * 2007-08-06 2009-02-26 Seiko Epson Corp 半導体装置および電気光学装置

Also Published As

Publication number Publication date
US8530333B2 (en) 2013-09-10
JP2010239123A (ja) 2010-10-21
US20100230754A1 (en) 2010-09-16
CN101840864B (zh) 2016-03-02
CN101840864A (zh) 2010-09-22

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